P4C198/P4C198L, P4C198A/P4C198AL
ULTRA HIGH SPEED 16K x 4
STATIC CMOS RAMS
FEATURES
Output Enable & Chip Enable Control Functions
Full CMOS, 6T Cell
– Single Chip Enable P4C198
– Dual Chip Enable P4C198A
High Speed (Equal Access and Cycle Times)
– 10/12/15/20/25 ns (Commercial)
– 12/15/20/25/35 ns (Industrial)
Common Inputs and Outputs
– 15/20/25/35/45 ns (Military)
Fully TTL Compatible Inputs and Outputs
Low Power Operation (Commercial/Military)
5V ± 10% Power Supply
Standard Pinout (JEDEC Approved)
– 24-Pin 300 mil DIP
– 24-Pin 300 mil SOJ
– 28-Pin 350 x 550 mil LCC
Data Retention, 10 µA Typical Current from 2.0V
P4C198L/198AL(Military)
DESCRIPTION
TheP4C198/LandP4C198A/Lare65,536-bitultrahigh-
speed static RAMs organized as 16K x 4. Each device
featuresanactivelowOutputEnablecontroltoeliminate
data bus contention. The P4C198/L also have an active
lowChipEnable(theP4C198A/LhavetwoChipEnables,
both active low) for easy system expansion. The CMOS
memoriesrequirenoclocksorrefreshingandhaveequal
access and cycle times. Inputs are fully TTL-compatible.
The RAMs operate from a single 5V ± 10% tolerance
power supply. Data integrity is maintained with supply
voltages down to 2.0V. Current drain is typically 10 µA
from a 2.0V supply.
Access times as fast as 12 nanoseconds are available,
permitting greatly enhanced system operating speeds.
CMOSisusedtoreducepowerconsumptiontoalow715
mW active, 193 mW standby.
The P4C198/L and P4C198A/L are available in 24-pin
300 mil DIP and SOJ, and 28-pin 350 x 550 mil LCC
packages providing excellent board level densities.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
DIP (P4, C4, D4),
LCC (L5)
SOJ (J4)
P4C198 (P4C198A)
P4C198(P4C198A)
Document # SRAM113 REV A
Revised October 2005
1
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
