P4C1049/P4C1049L
HIGH SPEED 512K x 8
STATIC CMOS RAM
FEATURES
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
High Speed (Equal Access and Cycle Times)
— 15/20/25 ns (Commercial)
— 20/25/35 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
—36-Pin SOJ (400 mil)
—36-Pin FLATPACK
Single 5V±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
—36-Pin LCC (452 mil x 920 mil)
Common Data I/O
Three-State Outputs
DESCRIPTION
The P4C1049 device provides asynchronous operation
with matching access and cycle times. Memory loca-
tions are specified on address pinsA0 toA18. Reading is
accomplished by device selection (CE) and output en-
abling (OE) while write enable (WE) remains HIGH. By
presenting the address under these conditions, the data
in the addressed memory location is presented on the
data input/output pins. The input/output pins stay in the
HIGH Z state when either CE or OE is HIGH or WE is
LOW.
The P4C1049 is a 4 Megabit high-speed CMOS
static RAM organized as 512Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 15 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The P4C1049
is a member of a family of PACE RAM™ products offer-
ing fast access times.
PIN CONFIGURATIONS
FUNCTIONAL BLOCK DIAGRAM
SOLDER-SEAL
FLATPACK (FS-4)
SOJ (J9)
LCC (L11)
1519B
Document # SRAM128 REV OR
Revised October 2005
1
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
