P4C1048L
LOW POWER 512K x 8
CMOS STATIC RAM
FEATURES
Common Data I/O
V
CC Current
Three-State Outputs
— Operating: 35mA
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
— CMOS Standby: 100µA
Access Times
—45/55/70/100 ns
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE and OE
Inputs
—32-Pin TSOP II
DESCRIPTION
The P4C1048L is a 4 Megabit low power CMOS static
RAM organized as 512K x 8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
locations are specified on address pinsA0 toA18. Read-
ing is accomplished by device selection (CE low) and
output enabling (OE) while write enable (WE) remains
HIGH. By presenting the address under these condi-
tions, the data in the addressed memory location is pre-
sented on the data input/output pins. The input/output
pins stay in the HIGH Z state when either CE is HIGH or
WE is LOW.
Access times as fast as 45 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1048L is packaged in a 32-pin 445 mil plastic
SOP, 32-pin TSOP II, or 600 mil plastic or ceramic side-
brazed DIP.
The P4C1048L device provides asynchronous opera-
tion with matching access and cycle times. Memory
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DIP (P600, C10),
SOP (S12), TSOP II (T4)
TOP VIEW
Document # SRAM129 REV D
Revised July 2007
1
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
