P4C1026
ULTRA HIGH SPEED 256K x 4
STATIC CMOS RAM
FEATURES
TTL/CMOSCompatibleOutputs
Fully TTL Compatible Inputs
Full CMOS, 6T Cell
High Speed (Equal Access and Cycle Times)
–15/20/25/35ns(Commercial/Industrial)
– 20/25/35 ns (Military)
StandardPinout(JEDECApproved)
– 28-Pin 300 mil SOJ
Low Power
– 28-Pin 400 mil SOJ
– 28-Pin 400 mil Ceramic DIP
– 32-Pin Ceramic LCC
Single 5V±10% Power Supply
Data Retention with 2.0V Supply
Three-StateOutputs
DESCRIPTION
Access times as fast as 15 nanoseconds are available,
permitting greatly enhanced system speeds. CMOS is
utilized to reduce power consumption.
The P4C1026 is a 1 Meg ultra high speed static RAM
organizedas256Kx4.TheCMOSmemoryrequiresnoclock
orrefreshingandhasequalaccessandcycletimes. Inputs
and outputs are fully TTL-compatible. The RAM operates
fromasingle5V±10%tolerancepowersupply.Withbattery
backup,dataintegrityismaintainedforsupplyvoltagesdown
to 2.0V.
TheP4C1026is availableina28-pin300miland400milSOJ
packages, as well as Ceramic DIP and LCC packages,
providingexcellentboardleveldensities.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
SOJ (J5, J7), DIP (C7)
LCC(L13)
Document # SRAM127 REV E
Revised April 2007
1
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
