P4C1024L
LOW POWER 128K x 8
CMOS STATIC RAM
FEATURES
Common Data I/O
V
CC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Access Times
—55/70 (Commercial or Industrial)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using CE1, CE2 and OE
Inputs
Packages
—32-Pin 600 mil Plastic and Ceramic DIP
—32-Pin 445 mil SOP
—32-Pin TSOP
DESCRIPTION
The P4C1024Lis a 1,048,576-bit low power CMOS static
RAM organized as 128Kx8. The CMOS memory re-
quires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
locations are specified on address pinsA0 toA16. Read-
ing is accomplished by device selection (CE1 low and
CE2 high) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory lo-
cation is presented on the data input/output pins. The
input/output pins stay in the HIGH Z state when either
CE1 or OE is HIGH or WE or CE2 is LOW.
Access times of 55 ns and 70 ns are availale. CMOS is
utilized to reduce power consumption to a low level.
The P4C1024L is packaged in a 32-pin TSOP, 445 mil
SOP, and a 600 mil PDIP.
The P4C1024L device provides asynchronous opera-
tion with matching access and cycle times. Memory
PIN CONFIGURATION
FUNCTIONAL BLOCK DIAGRAM
DIP (P600, C10), SOP (S12)
TOP VIEW
See end of datasheet for TSOP pin configuration.
Document # SRAM125 REV C
Revised September 2006
1
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
