P3C1256L
LOW POWER 32K x 8
STATIC CMOS RAM
FEATURES
VCC Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
Access Times
—55/70/85
— 28-Pin 600 mil DIP
— 28-Pin 330 mil SOP
— 28-Pin TSOP
Wide Range Power Supply: 2.7V to 3.6V
Easy Memory Expansion Using CE and OE Inputs
Common Data I/O
DESCRIPTIOꢀ
The P3C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access and
cycle times. Inputs are fully TTL-compatible. The RAM
operates with a wide range power supply (2.7V to 3.6V).
with matching access and cycle times. Memory locations
are specified on address pinsA0 toA14. Reading is accom-
plished by device selection (CE and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE or OE is HIGH or WE is LOW.
Access times of 55 ns and 70 ns are available. CMOS is
utilized to reduce power consumption to a low level.
The P3C1256L device provides asynchronous operation
FUꢀCTIOꢀAL BLOCꢁ DIAꢂRAM
PIꢀ COꢀFIꢂURATIOꢀS
DIP (P6), SOP (S11-3)
TOP VIEW
Document # SRAM143 REV A
Revised October 2011
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
