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P1757ME-35QLM 参数 Datasheet PDF下载

P1757ME-35QLM图片预览
型号: P1757ME-35QLM
PDF下载: 下载PDF文件 查看货源
内容描述: 完整的嵌入式CPU子系统 [COMPLETE EMBEDDED CPU SUBSYSTEM]
分类和应用:
文件页数/大小: 34 页 / 651 K
品牌: PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
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PACE 1757 M/ME  
TIMING GENERATOR STATE DIAGRAMS  
Two separate and almost independent state diagrams  
may be used to describe the PACE1757ME machine  
cycle.  
The Execution Unit performs according to a cycle of  
three states represented by Diagram A (the A machine)  
and the External Bus Unit follows a minimum cycle of  
four states, indicated in Diagram B (the B machine).  
Referring to Diagram A, the paths are defined as  
follows for the Execution Unit:  
(0) External Reset true  
(1) External Reset false  
(2) ALU wait or Bus wait.  
(3) ALU Branch false  
(4) ALU Branch true  
Diagram A  
Diagram B defines the paths for the External Bus as  
follows:  
(0) External Rest false  
(1) No Internal Bus Req.  
(2) Internal Bus Req.  
(3) Bus Busy or No Bus Grant  
(4) Bus Grant and Not Busy or  
Bus Locked by CPU  
(5) RDYA false  
(6) RDYA true  
(7) RDYD false  
(8) RDYD true, and no Internal Bus Request  
(9) RDYD true, Internal Bus Request pending  
(10) Bus Locked by CPU and No Internal Request  
(11) Bus Locked by CPU Internal Req.  
Diagram B  
NOTE:  
Bus A = Bus grant and Bus not busy and Bus not locked.  
V
Do c um e nt # MICRO-10 REV B  
Pa g e 7 o f 34