PACE1753/SOS
PIN FUNCTIONS
Symbol
Name
Description
Active LOW inputs that indicate a requirement for the bus from 4
masters on the bus. The master assigned to pin BUS-REQ has
1
BUS REQ -
Bus Request
0
BUS REQ
3
0
highest priority; the master assigned to pin BUS-REQ has lowest
3
priority.
1
BUS LOCK
Bus Lock
An active LOW input that indicates that the one master assigned
the bus is using the bus. A new master will receive a bus grant only
after this signal becomes inactive.
1
BUS GNT -
Bus Grant
Active LOW outputs indicating which master was granted the
bus. It remains active during BUS LOCK unless a higher master
request occurs, which resets it. However, the higher master will be
granted the bus only after the present master’s BUS LOCK releases
the bus.
0
BUS GNT
3
M/IO
D/I
Memory or I/O
Data or Instruction
Read or Write
An input signal that indicates whether the current bus cycle is a
memory (HIGH) or l/O (LOW) cycle.
An input signal that indicates whether the current bus cycle access
is for data (HIGH) or instruction (LOW).
R/W
An input signal that indicates the direction of data flow on the bus.
A HIGH indicates a memory read or input operation into the master
and a LOW indicates a memory write or output operation from the
master.
STRBA
Address Strobe
An active HIGH input used to latch the address at the HIGH-to-
LOW transition of the strobe.
STRBD
Data Strobe
CPU Clock
An active LOW input used to strobe data in memory and I/O cycles.
CPU-CLK
A single-phase input clock signal (0-40MHz, 40% to 60% duty
cycle.)
RESET
Reset
An active LOW input that initializes the device.
AK - AK
Access Key
Active HIGH inputs used to match the access lock in the MMU page
for memory accesses. A mismatch will cause the MEM PRT ERR
signal to become active.
0
3
3
AS - AS
Address State
Active HIGH inputs that select the page register group in the MMU.
In the DMA physical demultiplexed mode, AS(0:1) will receive the
9th and 10th most significant bits of the physical address for use in
the BPU function.
0
EXT ADR -
Extended Addresses Bus A bi-directional active HIGH bus. In CPU cycles, it is an output
bus which is used to select one of 256 pages, 4K words each,
0
EXT ADR
7
expanding the direct addressing space to 1M word. In DMA cycles,
indicated by DMA-ACK being active, it is also an output bus except
when programmed for the physical demultiplexed DMA mode. In
this case it becomes an input to receive the 8 most significant bits
of the DMA physical address for use in the BPU function.
IB - IB
Information Bus
An active HIGH bi-directional time multiplexed address/data bus.
0
15
IB is the most significant bit.
0
EDC - EDC
Detection/Correction
Bus
An active HIGH bi-directional bus used for detection of errors on
0
5
the data bus (IB - IB ) and correction of single errors. When
0
15
working in parity mode EDC is the parity bit. EDC - EDC are
0
0
5
undefined in this case.
Do c um e nt # MICRO-8 REV B
Pa g e 11 o f 17
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
