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P1753S-20CMB 参数 Datasheet PDF下载

P1753S-20CMB图片预览
型号: P1753S-20CMB
PDF下载: 下载PDF文件 查看货源
内容描述: [Memory Management Unit, 16-Bit, 256 Pages, CMOS, DIP-64]
分类和应用: 时钟外围集成电路
文件页数/大小: 17 页 / 157 K
品牌: PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
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PACE1753/SOS  
AC ELECTRICAL CHARACTERISTICS  
(V = 4.5V)  
CC  
20 MHz  
25MHz  
30 MHz  
Symbol  
Parameter  
MMU Cache Hit  
TSTRBD (EXT ADR ERR) External Address Error  
Min Max Min Max Min Max Unit  
TD/I (EXT ADR)  
27  
37  
23  
33  
21  
30  
ns  
ns  
V
L
TC (IBD CORR)  
IBD (SING ERR)  
Error Correction Read Cycle  
Error Correction Read Cycle  
32  
37  
28  
33  
26  
31  
ns  
ns  
V
H
TC (SING ERR)  
Error Correction Read Cycle  
EDAC or Parity Write Cycle  
MMU Cache Miss  
27  
32  
27  
27  
36  
27  
34  
34  
34  
34  
32  
40  
36  
64  
27  
37  
27  
52  
42  
67  
52  
38  
23  
28  
23  
23  
32  
23  
30  
30  
30  
30  
28  
38  
32  
60  
23  
33  
23  
48  
38  
63  
48  
34  
21  
26  
21  
21  
30  
21  
28  
28  
28  
28  
26  
36  
30  
58  
21  
31  
21  
46  
36  
61  
46  
32  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
L
TIBD (EDC GEN)  
V
V
TSTRBD (EX RDY)  
L
TC (EX RDY)  
MMU Cache Miss  
H
TC (WR PROT)  
MMU Cache Miss  
L
TSTRBD (WR PROT)  
MMU Cache Miss  
H
H
TC (GNT1)  
TC (GNT0)  
TC (GNT0)  
TC (GNT1)  
Arbiter LOW to HIGH Priority  
Arbiter LOW to HIGH Priority  
Arbiter HIGH to LOW Priority  
Arbiter HIGH to LOW Priority  
Address Ready  
H
L
H
L
TC (RDYA)  
TFC (IB OUT)  
Clock to IB Out Valid (I/O Read)  
Parity Mode  
V
TIBD (MEM PAR ERR)  
IN  
TC (MEM PRT ERR)  
TSTRBD (WR PROT)  
Memory Protect Error  
Write Protect Cache Hit  
Write Protect Cache Miss  
Write Protect Cache Miss  
Cache Hit (BPU Protection Error)  
Cache Hit (MMU Key-Lock Error)  
Cache Miss (BPU Protection Error)  
Cache Hit (MMU Key-Lock Error)  
Clock to EXT ADR Valid (Miss)  
TC (WR PROT)  
L
TSTRBD (WR PROT)  
H
H
TD/I (PROT FLAG)  
TD/I (PROT FLAG)  
TC (PROT FLAG)  
TC (PROT FLAG)  
TC (EXT ADR)  
Notes:  
1. 4.5V V 5.5V, –55°C T +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.  
CC  
C
2. V = –3.0V for pulse widths less than or equal to 20ns.  
IL  
3. Duration of the short should not exceed one second; only one output may be shorted at a time.  
4. Pulse width of WR PROT/PROT FLAG shall be 80% of STRBD pulse width.  
5. Functional tests shall consist of the same functional tests used when testing the equivalent bulk CMOS, MIL-STD-883 compliant, Class B SMD  
5962-89505device.  
Do c um e nt # MICRO-8 REV B  
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