PACE1753
PIN FUNCTIONS (Continued)
Symbol
Name
Description
MEM PRT ERR Memory Protect Error
An active LOW output generated by the MMU or BPU blocks to
signal to the CPU a protected memory violation. The error is
generated in one of the following conditions: a mismatch in the
access keys in the MMU page, an access to an execution protected
page during instruction cycles, an access to a write-protected page
during data cycles, or an access to a page write-protected by the
BPU.
MEM PAR ERR Memory Parity Error
An active LOW output which signals to the CPU an error on the
data bus during a memory cycle. Two detection modes can be
selected by programming the control register: EDAC mode (6
Hamming code parity bits) or single bit parity mode (even or odd
parity). The signal is inactive when none of the above modes are
selected (default after Reset).
EXT ADR ERR
External Address Error
Single Error
An active LOW output which signals to the CPU an unimplemented
memory or illegal I/O access.
SING ERR
An active HIGH output to signal detection of a single error on the
data bus in memory cycles. It is high impedance when the EDAC
function is disabled by the program (default state after Reset).
RAM DIS
RAM-Disable
An active HIGH input from the P1754 device which enables the
corrected data on the data bus when the EDAC function is enabled.
An internal one clock delay is generated before the data is output
on the bus to allow external memory to disconnect itself from the
bus.
EX RDY
RDYA
Data Ready
An active HIGH output that indicates that no wait states are
requested. It becomes inactive for one clock (inserting one wait
state) whenever a memory page different than the current one is
accessed (causing a miss).
Address Ready
An active HIGH output that indicates that no wait states are
requested when STRBA is active. Wait states are inserted when
this signal becomes inactive during STRBA. Up to three wait states
can be inserted by programming an internal register. Three wait
states are inserted after Reset (default).
WR PROT/
PROT FLAG
Write Protected/
Protection Flag
Either an active LOW output (following STRBD timing) during legal
memory write cycles, when no protection error occurs, or an active
HIGH level indicating a protection error in a write cycle. Each mode
can be selected by programming the control register. Default mode
after Reset is write-protected.
DMA ACK
DMA Acknowledge
An active HIGH input from the DMA controller which indicates a
DMA cycle. Used to select the DMA table in the BPU memory for
protection. For example, this could allow the DMA channel to
update the program which could be write-protected from the
processor. In the physical DMA mode, it will cause the Extended
Address Lines (EXT ADR ) to become inputs, providing BPU
0-7
protection of the DMA transfers.
Note:
1. Used for Bus Arbitration; only available on 68-lead devices.
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