PACE1750A
SIGNAL DESCRIPTIONS
CLOCKS AND EXTERNAL REQUESTS
Mnemonic
Name
Description
CPU CLK
CPU clock
Asinglephaseinputclocksignal(0-40MHz, 40percentto60percentduty
cycle.
TIMER CLK
Timer clock
A 100 KHz input that, after synchronization with CPU CLK, provides the
clock for timer A and timer B. If timers are used, the CPU CLK signal
frequency must be > 300 KHz.
RESET
Reset
An active LOW input that initializes the device.
CON REQ
Console request
An active LOW input that initiates console operations after completion of
the current instruction.
INTERRUPT INPUTS
Mnemonic
Name
Description
PWRDN INT
Power down interrupt An interrupt request input that cannot be masked or disabled. This signal
is active on the positive going edge or the high level, according to the
interrupt mode bit in the configuration register.
USR INT -
User interrupt
Interrupt request input signals that are active on the positive going edge
or the high level, according to the interrupt mode bit in the configuration
register.
0
USR INT
5
IOL INT -
I/O level interrupts
Active HIGH interrupt request inputs that can be used to expand the
number of user interrupts.
1
IOL INT
2
FAULTS
Mnemonic
MEM PRT ER
Name
Description
Memory protect error
An active LOW input generated by the MMU or BPU, or both and sampled
by the BUS BUSY signal into the Fault Register (bit 0 CPU bus cycle, bit
1 if non-CPU bus cycle).
MEM PAR ER
EXT ADR ER
Memory parity error
AnactiveLOWinputsampledbytheBUSBUSYsignalintobit2ofthefault
register.
External address error An active LOW input sampled by the BUS BUSY signal into the Fault
register (bit 5 or 8), depending on the cycle (memory or I/O).
SYSFLT
SYSFLT
System fault ,
Asynchronous, positive edge-sensitive inputs that set bit 7 (SYSFLT )
0
0
1
0
System fault ,
or bits 13 and 15 (SYSFLT ) in the Fault register.
1
1
ERROR CONTROL
Mnemonic
Name
Description
UNRCV ER
Unrecoverable error
An active HIGH output that indicates the occurrence of an error classified
as unrecoverable.
MAJ ER
Major error
An active HIGH output that indicates the occurrence of an error classified
as major.
Do c um e nt # MICRO-3 Re v. C
Pa g e 12 o f 24
PYRAMID [ PYRAMID SEMICONDUCTOR CORPORATION ]
