AND1021ST/-EO
Intelligent Graphics Display
Block Diagram
8
D0-D7
8
I/O0-I/O7
RAM
12
AD0-AD12
R/W
CE
WR
RD
CE
C/D
RESET
HALT
HSCP
FR
LP
CDATA
Control Lines
X-Driver
X-Driver
T6963C
A0-A11
R/W
CE1
Because signal lines are directly connected
to C-MOS and are not pull-up or pull-down
internally, except RESET which is pull-up to
V
DD
, you must guard all signals from
external noise.
D0-D7
60
60
64
Y-Driver
LCD
V
EL
V
EL
Backlight
Dimensional Outline
EL Option Only
Ground
V
EL
7/20/07
Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085
Tel: 408.523.8200 • Fax: 408.733.1287 •
sales@purdyelectronics.com
• www.purdyelectronics.com
4
PURDY [ PURDY ELECTRONICS CORPORATION ]
