Displays
AND-TFT-070WL3
TFT Module Block Diagram
Timing Parameters - Interface Timing
Item
Power Supply
Symbol
VCC
1/tc
Min.
3.0
–
–
–
–
–
–
–
–
–
10
0
Typ.
3.3
32
31.25
33
1056
800
128
86
Max.
3.6
–
–
–
–
–
–
Unit
V
MHz
ns
us
tc
tc
tc
tc
tc
CLK
Frequency
tc
Period
Hp
Display Period
Pulse Width
Back-porch
Front-porch
Hpw+Hbp
Hdp
Hpw
Hbp
Hfp
–
HSYNC
–
–
–
42
214
–
tc
ns
tc
Hsync-CLK
Vsynch-Hsync
Hhc
Hvh
Tc-10
200
0
–
–
–
–
–
–
–
860
–
17.325
525
480
2
33
10
–
–
–
–
–
–
–
1064
–
–
ms
Hp
Hp
Hp
Hp
Hp
Hp
tc
Period
Vp
Display period
Pulse width
Back-porch
Front-porch
Vpw+Vbp
Vdp
Vpw
Vbp
Vfp
–
T1
T2
T3
T4
VSYNC
35
Horizontal scanning period
Horizontal disp;lay period
Vertical display period
Frame cycling period
CLK-DATA
1056
800
480
525
–
tc
DENB
–
T1
T1
ns
ns
520
10
8
800
–
–
Dcd
Dde
R, G, B
DATA-CLK
–
Purdy Electronics Corporation • 720 Palomar Avenue • Sunnyvale, CA 94085
Tel:408.523.8200 • Fax:408.733.1287 • sales@purdyelectronics.com • www.purdyelectronics.com
11/21/08
5
PURDY [ PURDY ELECTRONICS CORPORATION ]
