ASM705/706/707/708
ASM813L
April 2008
rev 1.6
WDO will also become LOW and remain so, whenever
the supply voltage, VCC , falls below the device threshold
level. WDO goes HIGH as soon as VCC transitions above
the threshold. There is no minimum pulse width for WDO
as there is for the RESET outputs. If WDI is floated, WDO
essentially acts as a low-power output indicator.
Monitoring Voltages Other Than VCC
The ASM705-708 can monitor voltages other than VCC
using the Power Fail circuitry. If a resistive divider is
connected from the voltage to be monitored to the Power
Fail input (PFI), the PFO will go LOW if the voltage at PFI
goes below 1.25V reference. Should hysteresis be
desired, connect a resistor (equal to approximately 10
times the sum of the two resistors in the divider) between
the PFI and PFO pins. A capacitor between PFI and GND
will reduce circuit sensitivity to input high-frequency
noise. If it is desired to assert a RESET for voltages other
than VCC then the PFO output is to be connected to the
MR.
Application Information
Ensuring That RESET is Valid Down to VCC = 0V
When VCC falls below 1.1V, the ASM705-708 RESET
output no longer pulls down; it becomes indeterminate.
To avoid the possibility that stray charges build up and
force RESET to the wrong state, a pull-down resistor
should be connected to the RESET pin, thus draining
such charges to ground and holding RESET low. The
resistor value is not critical. A 100kΩ resistor will pull
RESET to ground without loading it.
Bi-directional Reset Pin Interfacing
The ASM705/6/7/8 can interface with µP/µC bi-directional
reset pins by connecting a 4.7kΩ resistor in series with
the RESET output and the µP/µC bi-directional RESET
pin.
Low Power µP Supervisor Circuits
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Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
