ASM705/706/707/708
ASM813L
April 2008
rev 1.6
Detailed Description
A
proper reset input enables a microprocessor /
microcontroller to start in a known state. ASM70X and
ASM813L assert reset to prevent code execution errors
during power-up, power-down and brown-out conditions.
RESET/RESET Timing
The RESET/RESET signals are designed to start a
µP/µC in a known state or return the system to a known
state.
The ASM707/708 have two reset outputs, one active-
HIGH RESET and one active-LOW RESET output. The
ASM813L has only an active-HIGH output. RESET is
simply
the
complement
of
RESET.
Manual Reset (MR)
RESET is guaranteed to be LOW with VCC above 1.2V.
During a power-up sequence, RESET remains low until
the supply rises above the threshold level, either 4.65V or
4.40V. RESET goes high approximately 200ms after
crossing the threshold.
The active-LOW manual reset input is pulled high by a
250µA pull-up current and can be driven low by
CMOS/TTL logic or a mechanical switch to ground. An
external debounce circuit is unnecessary since the
140ms minimum reset time will debounce mechanical
pushbutton switches.
During power-down, RESET goes LOW as VCC falls
below the threshold level and is guaranteed to be under
0.4V with VCC above 1.2V.
By connecting the watchdog output (WDO) and MR, a
watchdog timeout forces RESET to be generated. The
ASM813L should be used when an active-HIGH RESET
is required.
In a brownout situation where VCC falls below the
threshold level, RESET pulses low. If a brown-out occurs
during an already initiated reset, the pulse will continue
for a minimum of 140ms.
Watchdog Timer
The watchdog timer available on the ASM705/706/813L
monitors µP/µC activity. An output line on the processor
is used to toggle the WDI line. If this line is not toggled
within 1.6 seconds, the internal timer puts the watchdog
output, WDO, into a LOW state. WDO will remain LOW
until a toggle is detected at WDI.
Power Failure Detection With Auxiliary Comparator
All devices have an auxiliary comparator with 1.25V trip
point and uncommitted output (PFO) and noninverting
input (PFI). This comparator can be used as a supply
voltage monitor with an external resistor voltage divider.
The attenuated voltage at PFI should be set just below
the 1.25 threshold. As the supply level falls, PFI is
reduced causing the PFO output to transit LOW. Normally
PFO interrupts the processor so the system can be shut
down in a controlled manner.
If WDI is floated or connected to a three-stated circuit, the
watchdog function is disabled, meaning, it is cleared and
not counting. The watchdog timer is also disabled if
RESET is asserted. When RESET becomes inactive and
the WDI input sees a high or low transition as short as
50ns, the watchdog timer will begin a 1.6 second
countdown. Additional transitions at WDI will reset the
watchdog timer and initiate a new countdown sequence.
Low Power µP Supervisor Circuits
4 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
