May 2007
rev 0.4
ASM3P622S00A/B/J/E/K
Input-Output Skew
Test Circuit
Timing-Safe™
Output
+3.3V
Input
VDD
0.1uF
0.1uF
LOAD
OUTPUT
TSKEW
+
TSKEW
-
+3.3V
VDD
GND
One clock cycle
N=1
T
SKEW represents input-output skew
when spread spectrum is ON
For example, TSKEW = ± 0.125 for an
Input clock12MHz, translates in to
(1/12MHz) * 0.125=10.41nS
A Typical example of Timing-Safe™ waveform
Input
Input
CLKOUT with SSOFF
Timing-Safe™ CLKOUT
Low Frequency Timing-Safe™ Peak EMI Reduction IC
8 of 16
Notice: The information in this document is subject to change without notice.