Octoberr 2003
rev 1.0
Block Diagram
D_C
PD# SRS
VDD
ASM3P1819A-H
Modulation
XIN
Crystal
Oscillator
XOUT
Feedback
Divider
Frequency
Divider
Phase
Detector
Loop
Filter
PLL
VCO
Output
Divider
ModOUT
REF
VSS
Pin Diagram
XIN
VSS
SRS
ModOUT
1
2
3
4
8
7
6
5
XOUT
VDD
PD#
REF
XIN
VSS
D_C
ModOUT
1
2
3
4
8
7
6
5
XOUT
VDD
PD#
REF
ASM3P1819A-D
ASM3P1819E-H
Pin Description
Pin Name
ASM3P1819A-D
ASM3P1819E-H
Pin#
1
2
3
XIN
VSS
D_C
Type
XIN
VSS
I
P
I
Description
Connect to externally generated clock signal or crystal.
Ground to entire chip.
Digital logic input used to select Down (LOW) or Center
(HIGH) spread options (Refer
Spread Deviation
Selection Table.)
This pin has an internal pull-up
resistor.
Spread range select. Digital logic input used to select
frequency deviation (Refer
Spread Deviation Selection
Table.)
Spread spectrum clock output.
Un-modulated reference output clock of the input
frequency.
Power-Down control pin. Pull LOW to enable Power-
Down mode. This pin has an internal pull-up resistor.
Connect to +3.3V.
Crystal connection. If connected to an externally
generated clock, this pin must be left unconnected.
3
4
5
6
7
8
ModOUT
REF
PD#
VDD
XOUT
SRS
ModOUT
REF
PD#
REF
XOUT
I
O
O
I
P
O
Low EMI Clock for Mobile VGA
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
