November 2006
rev 0.2
Pin Configuration
Top View – TSSOP Package
ASM2P5T9070A
GL
V
DD
V
DD
GND
GND
G1
V
DD
Q2
Q1
GND
V
DD
GND
A
V
DD
GND
Q10
Q9
V
DD
G2
GND
GND
V
DD
V
DD
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
GND
V
DD
V
DD
GND
GND
GND
V
DD
Q3
Q4
GND
V
DD
Q5
Q6
V
DD
GND
Q7
Q8
V
DD
V
DD
GND
GND
V
DD
GND
NC
ASM2P5T9070A
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Pin Description
Symbol
A
G1
G2
GL
Qn
V
DD
GND
NC
I/O
I
I
I
I
O
Type
LVTTL
LVTTL
LVTTL
LVTTL
LVTTL
PWR
PWR
Description
Clock input
Gate for outputs Q1 through Q5. When
G1
is LOW, these outputs are enabled. When G1
is HIGH, these outputs are asynchronously disabled to the level designated by GL
1
.
Gate for outputs Q6through Q10. When
G2
is LOW, these outputs are enabled. When G2
is HIGH, these outputs are asynchronously disabled to the level designated by GL
1
.
Specifies output disable level. If HIGH, the outputs disable HIGH. If LOW, the outputs
disable LOW.
Clock outputs
Power supply for the device core, inputs, and outputs
Power supply return for power
NOTE: Because the gate controls are asynchronous, runt pulses are possible. It is the user's responsibility to either time the gate control signals to minimize the
possibility of runt pulses or be able to tolerate them in down stream circuitry.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
