November 2006
rev 0.2
Power Supply Characteristics
Symbol
I
DDQ
I
DDD
I
TOT
ASM2P5T9070A
Parameter
Quiescent V
DD
Power Supply
Current
Dynamic V
DD
Power Supply
Current per Output
Total Power V
DD
Supply
Current
Test Conditions
1
V
DD
= Max., Reference Clock = LOW
Outputs enabled, All outputs unloaded
V
DD
= Max., V
DD
= Max., C
L
= 0pF
V
DD
= 2.5V., F
REFERENCE CLOCK
= 100MHz,
C
L
= 15pF
V
DD
= 2.5V., F
REFERENCE CLOCK
= 200MHz,
C
L
= 15pF
Typ
1.5
150
70
100
Max
2
200
90
Unit
mA
µA/MHz
mA
150
NOTE:
1. The termination resistors are excluded from these measurements.
Input AC Test Conditions
Symbol
V
IH
V
IL
V
TH
t
R
, t
F
Input HIGH Voltage
Input LOW Voltage
Input Timing Measurement Reference Level
Input Signal Edge Rate
2
1
Parameter
Value
V
DD
0
V
DD
/2
2
Units
V
V
V
V/nS
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/nS or greater is to be maintained in the 10% to 90% range of the input waveform.
AC Electrical Characteristics Over Operating Range
4
Symbol
Skew Parameters
t
SK(O)
t
SK(P)
t
SK(PP)
t
PLH
t
PHL
t
R
t
F
f
O
t
PGE
t
PGD
Same Device Output Pin-to-Pin Skew
1
Pulse Skew
2
Part-to-Part Skew
3
25
300
300
pS
pS
pS
Parameter
Min
Typ
Max
Unit
Propagation Delay
Propagation Delay A to Qn
Output Rise Time (20% to 80%)
Output Fall Time (20% to 80%)
Frequency Range
Output Gate Enable to Qn
Output Gate Enable to Qn Driven to GL Designated Level
350
350
2
850
850
200
3.5
3
nS
pS
pS
MHz
nS
nS
Output Gate Enable/Disable Delay
NOTES:
1. Skew measured between all outputs under identical input and output transitions and load conditions on any one device.
2. Skew measured is the difference between propagation delay times t
PHL
and t
PLH
of any output under identical input and output transitions and load conditions
on any one device.
3. Skew measured is the magnitude of the difference in propagation times between any outputs of two devices, given identical transitions and load conditions at
identical V
DD
levels and temperature.
4. Guaranteed by design.
2.5V Single Data Rate 1:10 Clock Buffer Terabuffer
Notice: The information in this document is subject to change without notice.
4 of 9
PULSECORE [ PulseCore Semiconductor ]
