November 2006
rev 0.3
Pin Configuration
GND
V
DD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
DD
1G
2Y4
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
20
CLK
V
DD
V
DD
2Y0
2Y1
GND
GND
2Y2
2Y3
V
DD
V
DD
2G
ASM2P2310A
ASM2P2310A
19
18
17
16
15
14
13
Pin Description
Pin #
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Pin Name
GND
V
DD
1Y0
1Y1
1Y2
GND
GND
1Y3
1Y4
V
DD
1G
2Y4
2G
V
DD
V
DD
2Y3
2Y2
GND
GND
2Y1
2Y0
V
DD
V
DD
CLK
Type
P
P
O
O
O
P
P
O
O
P
I
O
I
P
P
O
O
P
P
O
O
P
P
I
Ground Pin
DC Power supply, 2.3 V – 3.6V
Buffered Output Clock
Buffered Output Clock
Buffered Output Clock
Ground Pin
Ground Pin
Buffered Output Clock
Buffered Output Clock
Description
DC power supply, 2.3V – 3.6V
Output enable control for 1Y[0:4] outputs.
meaning the 1Y[0:4] clock outputs follow the
high.
Buffered Output Clock
Output enable control for 2Y[0:4] outputs.
meaning the 2Y[0:4] clock outputs follow the
high.
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Buffered Output Clock
Buffered Output Clock
Ground Pin
Ground Pin
Buffered Output Clock
Buffered Output Clock
DC power supply, 2.3V – 3.6V
DC power supply, 2.3V – 3.6V
Input reference frequency
This output enable is active-high,
input clock (CLK) if this pin is logic
This output enable is active-high,
input clock (CLK) if this pin is logic
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
