November 2006
rev 0.3
Timing Requirements
Over recommended ranges of supply voltage and operating free-air temperature
ASM2P2310A
Symbol
f
clk
Parameter
Clock frequency
Test Conditions
V
DD
= 3 V to 3.6V
V
DD
= 2.3 V to 2.7V
Min
0
0
Typ
Max
200
170
Unit
MHz
Switching Characteristics
Over recommended operating free-air temperature range (unless otherwise noted)
V
DD
= 3.3 V
±
0.3 V
(See Figure 2)
Symbol
t
PLH
t
PHL
t
sk(o)
t
sk(p)
t
sk(pp)
t
r
t
f
t
su(en)
t
su(dis)
t
h(en)
t
h(dis)
Parameter
CLK to Yn
Output skew (Ym to Yn)
1
(see Figure 4)
Pulse skew (see Figure 5)
Part-to-part skew
Rise time (see Figure 3)
Fall time (see Figure 3)
Enable setup time,G_high before CLK↓
Disable setup time, G_low before CLK↓
Enable hold time, G_high after CLK
↓
Disable hold time, G_low after CLK
↓
Test Conditions
f = 0 MHz to 200 MHz
For circuit load,
see Figure 2.
Min
1.3
Typ
Max
2.8
100
250
500
Unit
nS
pS
pS
pS
V/nS
V/nS
nS
nS
nS
nS
V
O
= 0.4V to 2V
V
O
= 2 V to 0.4V
0.7
0.7
0.1
0.1
0.4
0.4
2
2
Note: 1 The t
sk(o)
specification is only valid for equal loading of all outputs
V
DD
= 2.5 V
±
0.2 V
(See Figure 2)
Symbol
t
PLH
Parameter
CLK to Yn
Test Conditions
f = 0MHz to 170MHz
For circuit load,
see Figure 2.
Min
1.5
Typ
Max
3.5
170
400
600
Unit
nS
pS
pS
pS
V/nS
V/nS
nS
nS
nS
nS
t
PHL
t
sk(o)
t
sk(p)
t
sk(pp)
t
r
t
f
t
su(en
t
su(dis)
t
h(en)
t
h(dis)
1
Output skew (Ym to Yn) (see Figure 4)
Pulse skew (see Figure 5)
Part-to-part skew
Rise time (see Figure 3)
Fall time (see Figure 3)
Enable setup time,G_high before CLK↓
Disable setup time, G_low before CLK↓
Enable hold time, G_high after CLK
↓
Disable hold time, G_low after CLK
↓
V
O
= 0.4V to 1.7V
V
O
= 1.7V to 0.4V
0.5
0.5
0.1
0.1
0.4
0.4
1.4
1.4
Note: 1 The t
sk(o)
specification is only valid for equal loading of all outputs.
2.5-V TO 3.3-V High-Performance Clock Buffer
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
