May 2005
rev 0.3
ASM2I99448
PCLK
VCC
VCC ÷2
GND
CCLK
VCMR
VPP
PCLK
VCC
VCC ÷2
GND
VCC
VCC ÷2
QX
QX
tP(LH)
GND
tP(LH)
tP(HL)
tP(HL)
Figure 11. Propagation Delay (tPD
) Test Reference
Figure 12. Propagation Delay (tPD
) Test Reference
VCC
VCC ÷2
GND
VCC
VCC ÷2
GND
CCLK
VCC
VCC ÷2
VCC
VCC ÷2
QX
GND
tSK(LH)
tSK(HL)
GND
tP(LH)
tP(HL)
The pin-to-pin skew is defined as the worst case
t
SK(P) =| tPHL - tPHL |
difference in propagation between any similar delay path
within a single device
Figure 14. Output Pulse Skew (tSK(P)
Test Reference
Figure 13. Output–to–Output Skew tSK(LH, HL)
VCC
V
GND
CC ÷2
VCC = 3.3V VCC = 2.5V
2.4
0.5
1.8V
0.6V
tP
tR
tF
T0
Figure 16. Output Transition Time Test Reference
DC (tP ÷T0 Χ 100%)
The time from the output controlled edge to the
non-controlled edge, divided by the time output
controlled edge, expressed as a percentage.
Figure 15. Output Duty Cycle (DC)
VCC
VCC ÷2
GND
CCLK
T
JIT(CC) = |TN -TN + 1|
VCC
VCC ÷2
TN
TN + 1
CLK_STOP
The variation in cycle time of a single between adjacent
cycles, over a random sample of adjacent cycle pairs
GND
tH
tS
Figure 17. Cycle–to–Cycle Jitter Reference
Figure 18. Setup and Hold Time (tS
, tH
) Test
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer
11 of 15
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
