July 2005
ASM2I99446
rev 0.4
Table 9: AC CHARACTERISTICS (VCC = VCCA = VCCB = VCCC = 2.5V ±5%, TA = –40°C to +85°C)1,2
Symbol
Characteristics
Min
Typ
Max
Unit
Condition
fref
Input Frequency
0
2503
MHz
÷1 output
÷2 output
0
2502
125
MHz
FSELx=0
FSELx=1
fMAX
Maximum Output Frequency
0
MHz
tP, REF
tr, tf
Reference Input Pulse Width
CCLK Input Rise/Fall Time
1.4
nS
nS
1.04
0.7 to 1.7V
tPLH
tPHL
tPLZ, HZ
CCLK0,1 to any Q
CCLK0,1 to any Q
2.6
2.6
5.6
nS
Propagation delay
5.5
nS
Output Disable Time
Output Enable Time
10
10
nS
nS
tPZL, LZ
Output-to-output Skew
Within one bank
150
200
350
pS
pS
pS
tsk(O)
Any output Bank, Same output divider
Any output, Any output divider
tsk(PP)
tSK(P)
Device-to-device Skew
Output pulse skew5
3.0
nS
200
pS
DCQ
tr, tf
Output Duty Cycle
÷1 or ÷2 output
45
0.1
50
55
1.0
%
nS
DCREF = 50%
0.6 to 1.8V
Output Rise/Fall Time
Note: 1 AC characteristics apply for parallel output termination of 50ꢀ to VTT
.
2 AC specifications are design targets, final specification is pending device characterization.
3 The ASM2I99446 is functional up to an input and output clock frequency of 350MHz and is characterized up to 250MHz.
4 Violation of the 1.0nS maximum input rise and fall time limit will affect the device propagation delay, device-to-device skew, reference input pulse width,
output duty cycle and maximum frequency specifications.
5 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
Table 10: AC CHARACTERISTICS (VCC = 3.3V + 5%, VCCA, VCCB, VCCC = 2.5V + 5% or 3.3V + 5%, TA = –40°C to +85°C)1,2
Symbol
Characteristics
Min
Typ
Max Unit
Condition
Output-to-output Skew
Within one bank
150
250
350
pS
pS
pS
tsk(O)
Any output Bank, Same output divider
Any output, Any output divider
tsk(PP)
Device-to-device Skew
2.5
nS
tPLH,HL
Propagation delay
Output pulse skew3
Output Duty Cycle
CCLK0,1 to any Q
÷1 or ÷2 output
See 3.3V table
tSK(P)
DCQ
250
pS
%
45
50
55
DCREF = 50%
Note: 1 AC characteristics apply for parallel output termination of 50ꢀ to VTT
.
2 For all other AC specifications, refer to 2.5V or 3.3V tables according to the supply voltage of the output bank.
3 Output pulse skew is the absolute difference of the propagation delay times: | tpLH - tpHL |.
2.5V and 3.3V LVCMOS Clock Distribution Buffer
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Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
