May 2005
ASM2I9942P
rev 0.3
Pin Diagram
24 23
22
21
20
19
18
17
GND
Q5
25
26
27
28
29
30
31
32
16
15
14
13
12
11
10
9
VCC
Q12
Q13
Q14
GND
Q15
Q16
Q17
Q4
Q3
ASM2I9942P
VCC
Q2
Q1
Q0
1
2
3
4
5
6
7
8
Table 2. Pin Description
Pin #
Pin Name
I/O
Type
Function
5
6
PECL_CLK,
PECL_CLK
Input
LVPECL
LVPECL Clock Inputs
Output enable/disable
3
OE
Input
-
LVCMOS
-
(high–impedance tristate)
4
NC
No connect
32,31,30,28,27,26,24,23,22,20,19,18,15,
14,13,11,10,9
Q0 – Q17
Output
LVCMOS Clock outputs
Negative power supply (GND)
1,2,12,17,25
GND
Supply
Ground
for I/O and core.
Positive power supply for I/O and
core. All VCC pins must be
connected to the positive power
supply for correct operation
7,8,16,21,29
VCC
Supply
VCC
Table 3. Absolute Maximum Rating1
Symbol
VCC
VI
IIN
Parameter
Min
–0.3
–0.3
Max
Unit
V
V
mA
°C
Supply Voltage
Input Voltage
Input Current
3.6
VCC + 0.3
±20
Storage Temperature Range
–40
125
TStor
Note: 1. These are stress ratings only and are not implied for functional use. Exposure to absolute maximum ratings for prolonged periods of time may affect
device reliability.
Low Voltage 1:18 Clock Distribution Chip
2 of 10
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
