January 2006
ASM2P20805A
rev 0.2
Test Circuits and Waveforms
2.5V
1.25V
0V
ENABLE
DISABLE
INPUT
2.5V
1.25V
0V
CONTROL
INPUT
tPZL
1.25V
tPLZ
VOH
Package 1
OUTPUT
VOH
OUTPUT
NORMALLY
LOW
1.25V
SWITCH
CLOSED
0.3V
0.3V
tPHZ
tPZH
Package 2
OUTPUT
1.25V
OUTPUT
NORMALLY
HIGH
SWITCH
OPEN
VOH
VOL
1.25V
VOL
tSK(PP)
= | tPLH2
- tPLH1
| or | tPHL2
- tPHL1
Enable and Disable Times
Note: 1. Diagram shown for input Control Enable-LOW and input Control
Note: Part-to- Part Skew is for package and speed grade.
Disable-HIGH
2.5V
2.5V
INPUT
INPUT
1.25V
0V
1.25V
0V
tPHL
tPHL
tPLH
tPLH
VOH
VOH
1.7V
0.7V
OUTPUT
OUTPUT
1.25V
VOL
1.25V
VOL
tSK(P) = | tPLH - tPLH
|
tR
tF
Pulse Skew
Propagation Delay
2.5V CMOS Dual 1-To-5 Clock Driver
7 of 12
Notice: The information in this document is subject to change without notice.
PULSECORE [ PulseCore Semiconductor ]
