October 2006
rev 1.6
Parameter
Watchdog Timeout Period
Watchdog Timeout Period
Output Voltage
Output Current
Output Current
Input Leakage
RESET Low Level
Internal Pull-up Resistor
Operating Current
Input Capacitance
Output Capacitance
PBRST Manual Reset
Minimum Low Time
Reset Active Time
I
CC1
C
IN
C
OUT
t
PB
t
RST
Must not exceed t
RD
mini-
ST Pulse Width
t
ST
mum. Watchdog cannot be
disabled.
Pulses < 2 µs at V
CCTP
min-
imum will not cause reset
20
20
PBRST = V
IL
20
250
610
Symbol
t
TD
t
TD
V
OH
I
OH
I
OL
I
IL
V
OL
Note 1
PBRST pin
Outputs open, V
CC
<= 3.6V
and all inputs at V
CC
or GND
40
Conditions
T
D
= VCC
T
D
Floating
I=-500µA, V
CC
< 2.7.V Note
1
Output = 2.4V, V
CC
>=2.7V
Output = 0.4V, V
CC
>=2.7V
10
-1.0
Min
500
250
V
CC
- 0.3V
Typ
1200
610
V
CC
- 0.1V
350
ASM1832
Max
2000
1000
Unit
ms
ms
V
µA
mA
1.0
0.4
µA
V
kΩ
20
5
7
µA
pF
pF
ms
1000
ms
ns
V
CC
Fail Detect to RESET or
RESET
V
CC
Slew Rate
PBRST Stable LOW to
RESET and RESET Active
V
CC
Detect to RESET or
RESET inactive
V
CC
Slew Rate
Notes
t
RPD
t
F
t
PDLY
t
RPU
t
R
5
8
µs
µs
20
ms
t
rise
=5µs
250
0
610
1000
ms
ns
1. RESET remains within 0.5V of V
CC
on power-down until V
CC
falls below 2V. RESET remains within 0.5V of ground on power-down until V
CC
falls below 2.0V.
3.3V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
6 of 9
PULSECORE [ PulseCore Semiconductor ]
