October 2003
ASM1817
rev 1.0
tR
Application Information
VCCTP (MAX)
Operation - Power Monitor
VCCTP
The ASM1817 detects out-of-tolerance power supply
conditions. It resets a processor during power-up, power-
down and issues a reset to the system processor when the
monitored power supply voltage is below the reset threshold.
When an out-of-tolerance VCC voltage is detected, the
VCCTP (MIN)
t
RESET signal is asserted. On power-up, RESET is kept
active (HIGH) for approximatley 150ms after the power
supply voltage has reached the selected tolerance. This
allows the power supply and microprocessor to stablize
before RESET is released.
RPU
VCC
VOL
RESET
Figure 2: Timing Diagram: Power-Up
ASM1817
Microprocessor
RESET
RESET
100kΩ
tF
VCC
VCCTP (MAX)
Figure 1: RESET Valid to 0V V
CC
VCCTP
VCCTP (MIN)
Output Conditions
The ASM1817 active LOW reset signal is valid as long as
VCC remains below 1.2V. The RESET output on the
tRPD
ASM1817 uses a push-pull drive stage that can maintain a
valid output below 1.2V. To sink current with VCC below 1.2V,
VOH
a resistor can be connected from the reset pin (RESET) to
Ground (see Figure 1). This configuration will give a valid
value on the RESET output with VCC approaching 0V. During
RESET Slews with VCC
RESET
Figure 3: Timing Diagram: Power-Down
both power up and down, this configuration will draw current
when the RESET is in the high state. A value of 100kΩ
should be adequate to maintain a valid connection.
3 of 8
Low Power, 3.3V/3.0V P Reset
Notice: The information in this document is subject to change without notice
PULSECORE [ PulseCore Semiconductor ]
