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ASM1232LPS-2F 参数 Datasheet PDF下载

ASM1232LPS-2F图片预览
型号: ASM1232LPS-2F
PDF下载: 下载PDF文件 查看货源
内容描述: 5V微处理器电源监控和复位电路 [5V μP Power Supply Monitor and Reset Circuit]
分类和应用: 电源电路电源管理电路微处理器复位电路光电二极管监控ISM频段
文件页数/大小: 10 页 / 281 K
品牌: PULSECORE [ PulseCore Semiconductor ]
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November 2006
rev 1.6
When PBRST is held LOW for the minimum time t
PB
, both
resets become active and remain active for a minimum time
period of 250ms after PBRST returns HIGH.
The debounced input is guaranteed to recognize pulses
greater than 20ms. No external pull-up resistor is required,
since PBRST is pulled HIGH by an internal 40kΩ resistor.
ST
ASM1232LP/LPS
power-up after the supply voltage returns to an in-tolerance
condition, the reset signal remains active for 250ms
minimum,
be detected.
Valid
Strobe
Valid
Strobe
Invalid
Strobe
allowing
the
power
supply
and
system
microprocessor to stabilize. ST pulses as short as 20ns can
The PBRST can be driven from a TTL or CMOS logic line or
shorted to ground with a mechanical switch.
t
PB
t
PDLY
V
IL
V
IH
RESET
t
ST
t
RST
t
TD
(min)
t
TD
(max)
~
~
PBRST
Note: ST is ignored whenever a reset is active
Figure 5: Timing Diagram: Strobe Input
Timeouts periods of approximately 150ms, 610ms or
1,200ms are selected through the TD pin.
V
OH
V
OL
~
~
t
RST
RESET
RESET
Figure 3: Timing Diagram: Pushbutton Reset
ASM1232LP/LPS
1
2
3
4
PBRST
TD
TOL
GND
V
CC
8
ST
RESET
RESET
Figure 4: Application Circuit: Pushbutton Reset
Watchdog Timer and ST Input
A watchdog timer stops and restarts a microprocessor that is
“hung-up”. The µP must toggle the ST input within a set
period (as selectable through TD input) to verify proper
software execution. If the ST is not toggled low within the
minimum timeout period, reset signals become active. In
~~
~~
5V
7
6
5
I/O
TD Voltage level
Watchdog Time-out Period
(ms)
Min
Nom
150
610
1200
Max
250
1000
2000
GND
Floating
V
CC
62.5
250
500
The watchdog timer can not be disabled. It must be strobed
µP
RESET
5V
with a high-to-low transition to avoid watchdog timeout and
reset.
ASM1232 LP/LPS
1
2
3
4
PBRST
T
D
TOL
GND
V
CC
8
ST
RESET
MREQ
10kΩ
7
6
5
µP
RESET
Address
Bus
Decoder
Figure 6: Application Circuit: Watchdog Timer
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
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