November 2006
rev 1.6
Parameter
Input Leakage
RESET Low Level
Internal Pull-up Resistor
Operating Current (CMOS)
Input Capacitance
Output Capacitance
PBRST Manual Reset
Minimum Low Time
Reset Active Time
ST Pulse Width
V
CC
Fail Detect to RESET or
RESET
V
CC
Slew Rate
PBRST Stable LOW to RESET and
RESET Active
V
CC
Detect to RESET or RESET
inactive
V
CC
Slew Rate
I
CC1
C
IN
C
OUT
t
PB
t
RST
t
ST
t
RPD
t
F
t
PDLY
t
RPU
t
R
t
RISE
= 5µs
4.25V to 4.75V
250
0
4.75V to 4.25V
300
Note 4
PBRST = V
IL
20
250
20
Symbol
I
IL
V
OL
Note 1
Note 3
Note 1
Conditions
Min
-1.0
ASM1232LP/LPS
Typ
Max
1.0
0.4
40
30
5
10
Unit
µA
V
kΩ
µA
pF
pF
ms
610
1000
ms
ns
5
8
µs
µs
20
610
1000
ms
ms
ns
Notes
1. PBRST is internally pulled HIGH to V
CC
through a nominal 40kΩ resistor.
2. RESET is an open drain output.
3. RESET remains within 0.5V of V
CC
on power-down until V
CC
falls below 2V. RESET remains within 0.5V of ground on power-down until V
CC
falls below 2.0V.
4. Must not exceed the minimum watchdog time-out period (t
TD
). The watchdogcircuit cannot be disabled. To avoid a reset, ST must be strobed.
5V µP Power Supply Monitor and Reset Circuit
Notice: The information in this document is subject to change without notice
6 of 10
PULSECORE [ PulseCore Semiconductor ]
