October 2003
rev 1.0
Block Diagram
P2040A
SR0 SR1 MRA SSON#
VDD
DIV2
Modulation
CLKIN
Frequency
Divider
Feedback
Divider
PLL
Phase
Detector
Loop
Filter
VCO
Output
Divider
ModOUT
VSS
Pin Configuration
CLKIN
MRA
SR1
VSS
1
2
8
7
VDD
SR0
ModOUT
SSON#
P2040A
3
4
6
5
Pin Description
Pin#
1
2
3
4
5
6
7
8
Pin
Name
CLKIN
MRA
SR1
VSS
SSON#
ModOUT
SR0
VDD
Type
I
I
I
P
I
O
I
P
Description
External reference frequency input. Connect to externally generated reference signal.
Digital logic input used to select modulation rate. This pin has an internal pull-up
resistor.
Digital logic input used to select Spreading Range. This pin has an internal pull-up
resistor.
Ground to entire chip. Connect to system ground.
Digital logic input used to enable Spread Spectrum function (Active LOW). Spread
Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal
pull-low resistor.
Spread spectrum clock output.
Digital logic input used to select Spreading Range. This pin has an internal pull-up
resistor.
Power supply for the entire chip (3.3V)
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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PULSECORE [ PulseCore Semiconductor ]
