Tel:886-2-66296288
Fax:886-2-29174598
URL:http://www.princeton.com.tw
LCD Driver IC
PT6584
t1 t2
t3 t4
V
V
DD
VDET
VDET
LC D
CE
V
IL
Display and control data transfer
D1 to D56
Inte rn al data
S0 , S1, K0 , K1
P0 to P2, SC , D R
Undefined
Defined
Defined
Defined
Undefined
Undefined
Undefined
Inte rn al da ta (D5 7 to D11 2)
In ternal d ata (D 113 to D 168 )
Undefined
Undefined
Undefined
Defined
Undefined
Inte rn al data (D1 69 to D22 0)
Sys tem reset period
t1
t2
t3
t4
≥
≥
≥
≥
1[m s] (Logic block power supply voltage VDD rise time)
0
0
1[m s] (Logic block pow er supply voltage VDD fall time)
Figure 3
PT6584 INTERNAL BLOCK STATES DURING THE RESET PERIOD
• CLOCK GENERATOR
Reset is applied and the base clock is stopped. However, the OSC pin state (normal or sleep mode)
is determined after the S0 and S1 control data bits are transferred.
• COMMON DRIVER, SEGMENT DRIVER & LATCH
Reset is applied and the display is turned off. However, display data can be input to the latch circuit
in this state.
• KEY SCAN
Reset is applied, the circuit is set to the initial state, and at the same time the key scan operation is
disabled.
• KEY BUFFER
Reset is applied and all the key data is set to low.
• CCB INTERFACE, CONTROL REGISTER, SHIFT REGISTER
Since serial data transfer is possible, these circuits are not reset.
PT6584 V1.1
- 23 -
August, 2006
PTC [ PRINCETON TECHNOLOGY CORP ]
