PT6312_10 参数 Datasheet PDF下载

Tel: 886-2-66296288

Fax: 886-2-29174598

URL: http://www.princeton.com.tw

VFD Driver/Controller IC

PT6312

SCANNING AND DISPLAY TIMING

The Key Scanning and display timing diagram is given below. One cycle of key scanning consists of 1

frame. The data of the 6 x 4 matrix is stored in the RAM.

T

DI SP L AY

= 500

µ

s

Key S can D ata

SG Output

G1

G2

G3

DIG1

DIG2

DIG3

DIGn

DIG1

Gn

1 F rame = T

D IS P LAY

x (n +1)

PT6312 V2.6

- 11 -

December, 2005