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URL: http://www.princeton.com.tw
Dot Character VFD Controller/Driver IC
PT6314
TIMING 2 REQUIREMENTS
(Unless otherwise specified, Ta=-40 To +85℃)
I80 Interface Parallel Data Transfer: Write (VDD1=5.0 10%)
Parameter
RS hold time
RS setup time
Symbol
tRH8
tRS8
tCYC8
tCCLW
tCCLR
tCCHW
tCCHR
tDS8
Condition
Min. Typ. Max. Unit
10
10
168
30
70
100
70
55
55
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
System cycle time
Control “L” pulse width (WR)
Control “L” pulse width (RD)
Control “H” pulse width (RD)
Control “H” pulse width (RD)
Data setup time
/WR
/RD
/WR
/RD
D0 to D7
Do to D7
Data hold time
RD access time
Output disable time
Reset pulse width
tDH8
tACC8
tOH8
Do to D7, CL=100pF
Do to D7, CL=100pF
70
-
5
tWRE
500
-
Parallel I/F (I80)
RS
tRHS
tr
tr
/CS
tCYCS
tRS8
tCCLR, tCCLW
tOSS
/WR, /RD
tCCHR, tCCHW
tOHS
tr
D0 to D7
(WRITE)
tOHS
tACCS
D0 to D7
(READ)
Notes:
1. Input signal rise time and fall time (tF, tR) < 15ns
2. All timing is specified using 0.20VDD1 and 0.80VDD1 as reference.
3. tCCLW and tCCLR are specified as the overlap between /CS=”L” /WR and /RD=”L”
PT6314 V1.3
- 37 -
March, 2006
PTC [ PRINCETON TECHNOLOGY CORP ]
