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Dot Character VFD Controller/Driver IC
PT6314
CPU INTERFACE (DATA TRANSFER)
M68 PARALLEL DATA TRANSFER
The M68 type of parallel data transfer is selected when IFSEL is set to “1” and MCU is set to “0” Under
this mode, the PT6314 can interface with the CPU in 4 or 8 bits . Please take note that the internal
registers are composed of 8 bits. During data transfer in 4 bits, DB4 to DB7 performs the data transfer
operation two times, the DB0 to DB3 must be set to either “H” or “L”. The higher order 4 bits (D4 to D7)
are initially transferred followed by the lower order 4 bits (D0 toD3). please refer to the diagrams below.
4-Bit M68 TYPE PARALLEL Data Transfer
RS
R/W
E
DB7
IR7
IR3
IR7
IR3
BF=0
IR3
D7
D3
IR6
IR5
IR2
IR1
IR6
IR5
IR2
IR1
IR6
IR5
IR2
IR1
D6
D5
D2
D1
DB6
DB5
DB4
IR4
IR0
IR4
IR0
IR4
IR0
D4
D0
Write Instruction
Write Instruction
Read Instruction
Write Data
PT6314 V1.3
- 19 -
March, 2006
PTC [ PRINCETON TECHNOLOGY CORP ]
