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Dot Character VFD Controller/Driver IC
PT6314
FUNCTION DESCRIPTION
BLOCK FUNCTIONS
CPU INTERFACE
PT6314 provides either 4 or 8 bits parallel or serial interface. These interface modes may be selected
using the IFSEL Pin (Pin No.24) as follows:
IFSEL Setting
Data Transfer Mode
Serial Data Transfer
Parallel Data Transfer
“0”
“1”
REGISTERS (INSTRUCTION REGISTER & DATA REGISTER)
PT6314 supports two 8-bit registers, namely: an Instruction Register (IR) and a Data Register (DR)
which may be selected using the Register Selector (RS) Signal. Please refer to Table below.
IFSEL
/CS
/CS
/CS
RS
STB
RS
E/SCK
SCK
E/(/RD)
R/W
*
R/D(/WR)
MCU
*
MCU
SI/SO
SI/SO
*
DBn
*
DBn
0
1
Note: *=This pin must be kept in either “HIGH” or “LOW” State.
The Instruction Register (IR) stores (1) instruction codes (i.e. display clear and cursor shift), (2) Display
Data RAM (DDRAM) Address Information and (3) Character Generator RAM (CGRAM). It can only be
written from the MCU.
The Data Register (DR) acts as a temporary storage for (1) data to be written into the DDRAM or
CGRAM and (2) data to be read from the DDRAM or CGRAM. Data written into the DR from the MCU
is automatically written into the DDRAM or CGRAM by internal operation. When the data stored in DR
is read by the MCU, data transfer is completed. After the completion of the data transfer (that is, after
the MCU has finished reading the first set of data), the DDRAM or CGRAM data in the next address is
sent to the DR. The MCU then again performs its Read operation for the next set of data.
PT6314 V1.3
- 13 -
March, 2006
PTC [ PRINCETON TECHNOLOGY CORP ]
