PE43711
UltraCMOS® RF Digital Step Attenuator
Table 7 • Serial Interface AC Characteristics(*)
Parameter/Condition
Min
Max
Unit
Serial clock frequency, FCLK
10
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Serial clock HIGH time, TCLKH
Serial clock LOW time, TCLKL
30
30
Last Serial clock rising edge setup time to Latch Enable rising edge, TLESU
Latch Enable minimum pulse width, TLEPW
Serial data setup time, TSISU
10
30
10
Serial data hold time, TSIH
10
Parallel data setup time, TDISU
Parallel data hold time, TDIH
100
100
100
100
100
100
Address setup time, TASU
Address hold time, TAH
Parallel/Serial setup time, TPSSU
Parallel/Serial hold time, TPSIH
Digital register delay (internal), TPD
10
Note: * V
= 3.3V or 5.0V, –40 °C < T < +105 °C, unless otherwise specified.
A
DD
Table 8 • Parallel and Direct Interface AC Characteristics(*)
Parameter/Condition
Min
Max
Unit
Latch Enable minimum pulse width, TLEPW
Parallel data setup time, TDISU
30
ns
ns
ns
ns
ns
ns
ns
100
100
100
100
Parallel data hold time, TDIH
Parallel/Serial setup time, TPSSU
Parallel/Serial hold time, TPSIH
Digital register delay (internal), TPD
Digital register delay (internal, direct mode only), TDIPD
10
5
Note: * V
= 3.3V or 5.0V, –40 °C < T < +105 °C, unless otherwise specified.
A
DD
Page 10
DOC-44414-2 – (3/2015)
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