PE43705
Product Specification
Typical Performance Data @ 25°C and VDD = 3.3V unless otherwise specified
Figure 23. Relative Phase Error vs.
Attenuation Setting
Figure 24. Relative Phase Error for 31.75 dB
Attenuation Setting vs. Frequency
70
60
50
40
30
20
10
0
100
80
60
40
20
0
0dB
0.9GHz
1.8GHz
2GHz
0.25dB
0.5dB
1dB
3GHz
4GHz
2dB
5GHz
4dB
6GHz
8dB
16dB
31.75dB
0
1
2
3
4
5
6
7
8
-40
25
85
Frequency (GHz)
Temperature (deg C)
Figure 25. Attenuation Error @ 900 MHz vs.
Temperature
Figure 26. Attenuation Error @ 1800 MHz vs.
Temperature
0.75
0.5
0.25
0
0.5
-40C
25C
-40C
25C
0.25
0
85C
85C
105C
105C
-0.25
-0.5
-0.25
-0.5
0
4
8
12
16
20
24
28
32
0
4
8
12
16
20
24
28
32
Attenuation Setting (dB)
Attenuation Setting (dB)
Figure 27. Attenuation Error @ 3000 MHz vs.
Temperature
Figure 28. IIP3 vs. Attenuation Setting
70
65
60
55
50
45
40
35
30
0.75
0.5
-40C
25C
0.00 dB Attn
0.25 dB Attn
0.50 dB Attn
1.00 dB Attn
2.00 dB Attn
4.00 dB Attn
8.00 dB Attn
16.00 dB Attn
31.75 dB Attn
0.25
0
85C
105C
-0.25
-0.5
0
4
8
12
16
20
24
28
32
2000
3000
4000
5000
Frequency (MHz)
6000
7000
8000
Attenuation Setting (dB)
©2013-2014 Peregrine Semiconductor Corp. All rights reserved.
Document No. DOC-47814-3 |
UltraCMOS® RFIC Solutions
Page 14 of 18
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