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PE42520 参数 Datasheet PDF下载

PE42520图片预览
型号: PE42520
PDF下载: 下载PDF文件 查看货源
内容描述: 的UltraCMOS RF SPDT开关在9 kHz - 13 GHz的 [UltraCMOS SPDT RF Switch 9 kHz - 13 GHz]
分类和应用: 开关光电二极管
文件页数/大小: 16 页 / 547 K
品牌: PSEMI [ Peregrine Semiconductor ]
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PE42520
Product Specification
Table 4. Absolute Maximum Ratings
Parameter/Condition
Supply voltage
Digital input voltage (CTRL)
LS input voltage
RF input power, CW
(RFC-RFX)
1
9 kHz
10 MHz
10 MHz
8 GHz
8 GHz
13 GHz
Symbol
V
DD
V
CTRL
V
LS
Min
-0.3
-0.3
-0.3
Max
5.5
3.6
3.6
Unit
V
V
V
Switching Frequency
The PE42520 has a maximum 25 kHz switching
rate when the internal negative voltage generator
is used (pin 13 = GND). The rate at which the
PE42520 can be switched is only limited to the
switching time (Table
1)
if an external negative
supply is provided (pin 13 = Vss
EXT
).
Switching frequency describes the time duration
between switching events. Switching time is the
time duration between the point the control signal
reaches 50% of the final value and the point the
output signal reaches within 10% or 90% of its
target value.
Optional External Vss Control (Vss
EXT
)
P
IN-CW
Fig. 4
36
Fig. 5
dBm
dBm
dBm
RF input power, pulsed
(RFC-RFX)
2
P
IN-PULSED
9 kHz
10 MHz
10 MHz
13 GHz
RF input power into terminated
ports, CW (RFX)
1
9 kHz
10 MHz
10 MHz
13 GHz
Storage temperature range
ESD voltage HBM
3
RF pins to GND
All pins
ESD voltage MM
4
, all pins
ESD voltage CDM
5
, all pins
P
IN,TERM
Fig. 4
Fig. 5
dBm
dBm
Fig. 4
26
-65
150
4000
2500
200
1000
dBm
dBm
°C
V
V
V
V
T
ST
V
ESD,HBM
V
ESD,MM
V
ESD,CDM
For proper operation, the Vss
EXT
control pin must
be grounded or tied to the Vss voltage specified in
Table 3.
When the Vss
EXT
control pin is grounded,
FETs in the switch are biased with an internal
negative voltage generator. For applications that
require the lowest possible spur performance,
Vss
EXT
can be applied externally to bypass the
internal negative voltage generator.
Spurious Performance
The typical spurious performance of the PE42520
is -152 dBm when Vss
EXT
= 0V (pin 13 = GND). If
further improvement is desired, the internal
negative voltage generator can be disabled by
setting Vss
EXT
= -3.4V.
Table 5. Control Logic Truth Table
LS
0
CTRL
0
1
0
1
RFC-RF1
off
on
on
off
RFC-RF2
on
off
off
on
Notes: 1. 100% duty cycle, all bands, 50Ω
2.
Pulsed, 5% duty cycle of 4620
µs
period, 50Ω
3. Human Body Model (MIL-STD 883 Method 3015)
4. Machine Model (JEDEC JESD22-A115)
5. Charged Device Model (JEDEC JESD22-C101)
Exceeding absolute maximum ratings may cause
permanent damage. Operation should be
restricted to the limits in the Operating Ranges
table. Operation between operating range
maximum and absolute maximum for extended
periods may reduce reliability.
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS
®
device, observe
the same precautions that you would use with
other ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the rating specified.
Latch-Up Avoidance
Unlike conventional CMOS devices, UltraCMOS
®
devices are immune to latch-up.
0
1
1
Moisture Sensitivity Level
The Moisture Sensitivity Level rating for the
PE42520 in the 16-lead 3x3 mm QFN package is
MSL3.
Logic Select (LS)
The Logic Select feature is used to determine the
definition for the CTRL pin.
Document No. DOC-12714-3 |
UltraCMOS
®
RFIC Solutions
©2012-2013 Peregrine Semiconductor Corp. All rights reserved.
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