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PS128128DRS-0 参数 Datasheet PDF下载

PS128128DRS-0图片预览
型号: PS128128DRS-0
PDF下载: 下载PDF文件 查看货源
内容描述: 外形尺寸与框图 [OUTLINE DIMENSION & BLOCK DIAGRAM]
分类和应用:
文件页数/大小: 65 页 / 1282 K
品牌: POWERTIP [ POWERTIP TECHNOLOGY ]
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ST7066U  
!"AC Characteristics  
(TA = 25, VCC = 2.7V)  
Symbol Characteristics  
Test Condition  
Min. Typ. Max. Unit  
Internal Clock Operation  
fOSC  
OSC Frequency  
R = 75KΩ  
190  
270  
350  
KHz  
External Clock Operation  
fEX  
External Frequency  
Duty Cycle  
-
-
-
125  
45  
-
270  
50  
-
410  
55  
KHz  
%
TR,TF  
Rise/Fall Time  
0.2  
µs  
Write Mode (Writing data from MPU to ST7066U)  
TC  
TPW  
TR,TF  
TAS  
Enable Cycle Time Pin E  
1200  
460  
-
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Enable Pulse Width Pin E  
Enable Rise/Fall Time Pin E  
25  
-
Address Setup Time Pins: RS,RW,E  
Address Hold Time Pins: RS,RW,E  
0
TAH  
10  
80  
10  
-
TDSW  
TH  
Data Setup Time  
Data Hold Time  
Pins: DB0 - DB7  
Pins: DB0 - DB7  
-
-
Read Mode (Reading Data from ST7066U to MPU)  
TC  
TPW  
TR,TF  
TAS  
Enable Cycle Time Pin E  
1200  
480  
-
-
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
ns  
Enable Pulse Width Pin E  
-
25  
-
Enable Rise/Fall Time Pin E  
Address Setup Time Pins: RS,RW,E  
Address Hold Time Pins: RS,RW,E  
0
TAH  
10  
-
-
TDDR  
TH  
Data Setup Time  
Data Hold Time  
Pins: DB0 - DB7  
Pins: DB0 - DB7  
320  
-
10  
Interface Mode with LCD Driver(ST7065)  
TCWH  
TCWL  
TCST  
TSU  
Clock Pulse with High Pins: CL1, CL2  
800  
800  
500  
300  
300  
0
-
-
-
-
-
-
-
ns  
ns  
ns  
ns  
ns  
ns  
Clock Pulse with Low Pins: CL1, CL2  
Clock Setup Time Pins: CL1, CL2  
-
-
Data Setup Time  
Data Hold Time  
M Delay Time  
Pin: D  
Pin: D  
Pin: M  
-
-
TDH  
TDM  
2000  
V2.0  
2001/03/01  
32/42  
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