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PS12801ARN-0 参数 Datasheet PDF下载

PS12801ARN-0图片预览
型号: PS12801ARN-0
PDF下载: 下载PDF文件 查看货源
内容描述: 外形尺寸与框图 [OUTLINE DIMENSION & BLOCK DIAGRAM]
分类和应用:
文件页数/大小: 65 页 / 1282 K
品牌: POWERTIP [ POWERTIP TECHNOLOGY ]
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ST7066U  
#" Read Busy Flag and Address  
RS  
0
RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
1
BF AC6 AC5 AC4 AC3 AC2 AC1 AC0  
Code  
When BF = “High”, indicates that the internal operation is being processed.So during this time the next  
instruction cannot be accepted.  
The address Counter (AC) stores DDRAM/CGRAM addresses, transferred from IR.  
After writing into (reading from) DDRAM/CGRAM, AC is automatically increased (decreased) by 1.  
#" Write Data to CGRAM or DDRAM  
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
Code  
1
0
D7 D6 D5 D4 D3 D2 D1 D0  
Write binary 8-bit data to DDRAM/CGRAM.  
The selection of RAM from DDRAM, CGRAM, is set by the previous address set instruction  
: DDRAM address set, CGRAM address set. RAM set instruction can also determine the AC  
direction to RAM.  
After write operation, the address is automatically increased/decreased by 1, according to  
the entry mode.  
#" Read Data from CGRAM or DDRAM  
RS RW DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0  
Code  
1
1
D7 D6 D5 D4 D3 D2 D1 D0  
Read binary 8-bit data from DDRAM/CGRAM.  
The selection of RAM is set by the previous address set instruction. If address set instruction of RAM is not  
performed before this instruction, the data that read first is invalid, because the direction of AC is not  
determined. If you read RAM data several times without RAM address set instruction before read operation,  
you can get correct RAM data from the second, but the first data would be incorrect, because there is no time  
margin to transfer RAM data.  
In case of DDRAM read operation, cursor shift instruction plays the same role as DDRAM address  
set instruction : it also transfer RAM data to output data register. After read operation address counter is  
automatically increased/decreased by 1 according to the entry mode. After CGRAM read operation, display  
shift may not be executed correctly.  
* In case of RAM write operation, after this AC is increased/decreased by 1 like read operation. In this time,  
AC indicates the next address position, but you can read only the previous data by read instruction.  
V2.0  
2001/03/01  
21/42  
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