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PG12864LRU-ORA-H-S0 参数 Datasheet PDF下载

PG12864LRU-ORA-H-S0图片预览
型号: PG12864LRU-ORA-H-S0
PDF下载: 下载PDF文件 查看货源
内容描述: 液晶显示模块 [LCD Module]
分类和应用:
文件页数/大小: 32 页 / 233 K
品牌: POWERTIP [ POWERTIP TECHNOLOGY ]
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NO.PG12864LRU-ORA-H Rev:0
(MPU timing characteristics)
(VDD=2.7 to 5.5V,Ta=-30 to +85℃)
Item
Address hold time
Address setup time
System cycle time
Road pulse width (READ)
Write pulse width (WRITE)
Data setup time
Data hold time
Read data output delay time
Read data hold time
Input signal rise and fall time
Item
Address hold time
Address setup time
System cycle time
Road pulse width (READ)
Write pulse width (WRITE)
Data setup time
Data hold time
Read data output delay time
Read data hold time
Input signal rise and fall time
Symbol
tAH8
tAS8
tCYC8
tRDW8
tWRW8
tDS8
tDH8
tRDD8
tRDH8
tr,tf
Symbol
tAH8
tAS8
tCYC8
tRDW8
tWRW8
tDS8
tDH8
tRDD8
tRDH8
tr,tf
CL=15pF
10
30
CL=15pF
10
Mesauring condition MIN MAX Unit
60
40
450
270
100
100
40
220
ns
ns
ns
ns
ns
ns
ns
ns
ns
Appllcable pin
CSB
RS
RDB
WRB
D0 to D7
D0 to D7
30
ns All of above pins
(VDD=2.4 to 2.7V,Ta=-30 to +85℃)
Mesauring condition MIN MAX Unit
80
80
900
500
200
200
80
320
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Appllcable pin
CSB
RS
RDB
WRB
D0 to D7
D0 to D7
All of above pins
. (VDD=1.8 to 2.4V,Ta=-30 to +85℃)
Item
Address hold time
Address setup time
System cycle time
Road pulse width (READ)
Write pulse width (WRITE)
Data setup time
Data hold time
Read data output delay time
Read data hold time
Input signal rise and fall time
Symbol
tAH8
tAS8
tCYC8
tRDW8
tWRW8
tDS8
tDH8
tRDD8
tRDH8
tr,tf
CL=15pF
10
30
Mesauring condition MIN MAX Unit
160
160
1800
1000
400
400
160
640
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
D0 to D7
All of above pins
Appllcable pin
CSB
RS
RDB
WRB
D0 to D7
Note:All the timings must be specified relative to 20% and 80% of VDD voltage
POWERTIP TECHNOLOGY CORPORATION
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