FIN1104
AC Electrical Characteristics
Over supply voltage and operating temperature ranges, unless otherwise specified
Symbol
t
PLHD
t
PHLD
t
TLHD
t
THLD
t
SK(P)
t
SK(LH)
,
t
SK(HL)
t
SK(PP)
f
MAX
t
PZHD
t
PZLD
t
PHZD
t
PLZD
t
DJ
t
RJ
Parameter
Differential Output Propagation Delay
LOW-to-HIGH
Differential Output Propagation Delay
HIGH-to-LOW
Differential Output Fall Time (80% to 20%)
Pulse Skew |t
PLH
- t
PHL
|
Channel-to-Channel Skew
(Note 4)
Part-to-Part Skew (Note 5)
Maximum Frequency (Note 6)(Note 7)
Differential Output Enable Time
from Z to HIGH
Differential Output Enable Time
from Z to LOW
Differential Output Disable Time
from HIGH to Z
Differential Output Disable Time
from LOW to Z
LVDS Data Jitter,
Deterministic
LVDS Clock Jitter,
Random (RMS)
V
ID
=
300 mV, PRBS
=
2
23
- 1,
V
IC
=
1.2V at 800 Mbps
V
ID
=
300 mV,
V
IC
=
1.2V at 400 MHz
R
L
=
100
Ω,
C
L
=
5 pF,
See Figure 2 and Figure 3
400
800
2.2
2.5
1.8
2.1
85
2.1
5
5
5
5
135
3.5
R
L
=
100
Ω,
C
L
=
5 pF,
V
IC
=
|V
ID
|/2 to V
CC
−
(|V
ID
|/2),
Duty Cycle
=
50%,
See Figure 1 and Figure 3
Differential Output Rise Time (20% to 80%) V
ID
=
200 mV to 450 mV,
Test Conditions
Min
Typ
(Note 3)
0.75
0.75
0.29
0.29
1.1
1.1
0.4
0.4
0.02
0.02
0.02
1.75
1.75
0.58
0.58
0.2
0.15
0.5
Max
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
ns
ns
ns
ps
ps
Note 3:
All typical values are at T
A
=
25°C and with V
CC
=
3.3V.
Note 4:
t
SK(LH)
, t
SK(HL)
is the skew between specified outputs of a single device when the outputs have identical loads and are switching in the same direc-
tion.
Note 5:
t
SK(PP)
is the magnitude of the difference in propagation delay times between any specified terminals of two devices switching in the same direction
(either Low-to-HIGH or HIGH-to-LOW) when both devices operate with the same supply voltage, same temperature, and have identical test circuits.
Note 6:
Passing criteria for maximum frequency is the output V
OD
>
200 mV and the duty cycle is 45% to 55% with all channels switching.
Note 7:
Output loading is transmission line environment only; C
L
is
<
1 pF of stray test fixture capacitance.
FIGURE 1. Differential Receiver Voltage Definitions and
Propagation and Transition Time Test Circuit
Note A: All LVDS input pulses have frequency
=
10 MHz, t
R
or t
F
< =
0.5 ns
Note B: C
L
includes all probe and test fixture capacitances
FIGURE 3. Differential Driver Propagation Delay
and Transition Time Test Circuit
FIGURE 2. Differential Driver DC Test Circuit
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