LNK403-409/413-419
Layout Considerations
components that connect to the SOURCE pin should follow the
same rules as the BYPASS pin capacitor. It is critical that the
main power FET switching currents return to the bulk capacitor
with the shortest path as possible. Long high current paths
create excessive conducted and radiated noise.
Primary Side Connections
Use a single point (Kelvin) connection at the negative terminal of
the input filter capacitor for the SOURCE pin and bias returns.
This improves surge capabilities by returning surge currents
from the bias winding directly to the input filter capacitor. The
BYPASS pin capacitor should be located as close to the
BYPASS pin and connected as close to the SOURCE pin as
possible. The SOURCE pin trace should not be shared with the
main power FET switching currents. All FEEDBACK pin
Secondary Side Connections
The output rectifier and output filter capacitor should be as
close as possible. The transformer’s output return pin should
have a short trace to the return side of the output filter capacitor.
Clamp
Bulk Capacitor
LNK403EG
FL1
6
1
R14
Input EMI Filter
2
VR1
R2
C2
Transformer
D1
C3
C8
L3
5
U1
C9
4
3
F1
T1
L1
L2
C7
C12
L
RV1
N
C5
R3
Output
VR3
C4
V
Filter
R24
C14
Capacitors
R16
C6
Copper Area for
Heat Sinking
R10
D8
V
BYPASS Pin
Capacitor
PI-5987-060110
Figure 12. RD-193 7 W Layout Example, Top Layer.
11
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Rev. D 08/11
POWERINT [ Power Integrations ]
