LCS700-708
PI-6469-062811
The recommended series resistor value of 220 W and the bypass
capacitor form a low-pass filter, and its time constant must not
cause significant attenuation of the current sense signal at the
nominal operating frequency. The effect of the attenuation is
greatest for the first pulse in the start-up current waveform, and
can also affect proper shutdown during short-circuit testing,
which typically trips the 7-cycle current limit. Place a close-
coupled probe across the IS pin bypass capacitor and compare
the waveform to the primary current.
24.1
24.0
23.9
400
300
200
100
0
Burst Mode Operation and Tuning
Burst mode will produce a typical waveform such as in Figure 24.
During the burst pulse train, the switching frequency rises from
fSTART to fSTOP
.
25
Time (μs)
50
0
LLC
Transformer
Figure 25. Zoom in of First Few Switching Cycles of Burst Pulse Train of Figure 24.
The First 2 Cycles Show That the High-Side Driver has not Turned
HB Pin
on yet. The Switching Frequency of the First Few Cycles is fSTART
335 kHz in This Case. The Ringing on the Output is from the
Output Filter.
,
If the initial output ripple spike at the beginning of the burst
pulse train is ignored, the output ripple somewhat resembles a
sawtooth. See the output ripple waveform in Figure 24. When
the HiperLCS is switching, the output rises. When it stops
switching, the output falls. The top of the sawtooth is where the
burst pulse train ends, because the feedback loop has commanded
a frequency = fSTOP. The bottom of the sawtooth is where the
burst pulse train begins, because the feedback loop has
commanded a frequency = fSTART. As such, the burst mode
control resembles a hysteretic controller, where the top and
bottom of the sawtooth are fixed by the feedback loop gain.
The downward slope of the sawtooth is merely the output
capacitors discharging into the load, with dv/dt:
C12
47 pF
1 kV
C11
6.8 nF
1 kV
IS Pin
R12
220 Ω
R11
24 Ω
C7
1 nF
GROUND
Pin
S Pin
PI-6161-051711
Figure 23. Capacitive Divider Current Sense Circuit.
dv
dt
#
I = C
PI-6468-062811
Where I = load current. C is the total output capacitance.
24.1
24.0
23.9
The upward slope of the sawtooth is dependent on the difference
between the current delivered by the powertrain, and the current
drawn by the load. For a given design, the upward slope
increases with input voltage.
400
300
200
100
0
The burst repetition rate (frequency) then increases with load.
When the load reaches a point where the powertrain can
regulate at a frequency <fSTOP, the bursting will stop. When the
load current decreases (from heavy load), frequency increases,
and when it reaches fSTOP, bursting will commence.
Burst Repetition Rate
In a typical design, fSTART must be chosen to be at least 20-40%
higher than the nominal switching frequency. Figure 18 shows
the relationship between fSTART and dead-time, and Table 5 the
ratio of fSTOP to fSTART vs. Burst Threshold setting number). In
some cases the designer may choose to change dead-time
slightly in order to change fSTART and fSTOP. Some designs may
only enter burst mode at zero load and an input voltage above
nominal.
50
100
0
Time (ms)
Figure 24. Typical Waveform of Burst Mode. 24 V / 150 W HiperLCS Design at
Zero Load. The Initial Spike (circled) Size is Dependent on Post-Filter
Electrolytic Capacitor ESR.
17
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Rev. B 062011
POWERINT [ Power Integrations ]
