InnoSwitch3-CP
FORWARD Pin Resistor
Note:
A 47 Ω, 5% resistor is recommended to ensure sufficient IC supply
current. A higher or lower resistor value should not be used as it can
affect device operation such as the timing of the synchronous rectifier
drive. Figures 13, 14, 15 and 16 below show examples of unacceptable
and acceptable FORWARD pin voltage waveforms. VD is forward
voltage drop across the SR.
If t1 + t2 = 1.5 ms ± 50 ns, the controller may fail the handshake and
trigger a primary bias winding OVP latch-off.
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Figure 16. Acceptable FORWARD Pin Waveform before Handshake with Body
Diode Conduction During Flyback Cycle.
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SR FET Operation and Selection
Although a simple diode rectifier and filter works for the output, use
of an SR FET enables the significant improvement in operating
efficiency often necessary to meet the European CoC and the U.S.
DoE energy efficiency requirements. The secondary-side controller
turns on the SR FET once the flyback cycle begins. The SR FET gate
should be tied directly to the SYNCHRONOUS RECTIFIER DRIVE pin
of the InnoSwitch3-CP IC (no additional resistors should be connected
in the gate circuit of the SR FET). The SR FET is turned off once the
VDS of the SR FET reaches 0 V.
Figure 13. Unacceptable FORWARD Pin Waveform After Handshake with
SR MOSFET Conduction During Flyback Cycle.
A FET with 18 mΩ RDS(ON) is appropriate for a 5 V, 2 A output, and a
FET with 8 mΩ RDS(ON) is suitable for designs rated with a 12 V, 3 A
output. The SR FET driver uses the SECONDARY BYPASS pin for its
supply rail, and this voltage is typically 4.4 V. A FET with a high
threshold voltage is therefore not suitable; FETs with a threshold
voltage of 1.5 V to 2.5 V are ideal although MOSFETs with a threshold
voltage (absolute maximum) as high as 4 V may be used provided
their data sheets specify RDS(ON) across temperature for a gate voltage
of 4.5 V.
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There is a slight delay between the commencement of the flyback
cycle and the turn-on of the SR FET. During this time, the body diode
of the SR FET conducts. If an external parallel Schottky diode is
used, this current mostly flows through the Schottky diode. Once the
InnoSwitch3-CP IC detects end of the flyback cycle, voltage across
SR FET RDS(ON) reaches 0 V, any remaining portion of the flyback cycle
is completed with the current commutating to the body diode of the
SR FET or the external parallel Schottky diode. Use of the Schottky
diode parallel to the SR FET may provide higher efficiency and
typically a 1 A surface mount Schottky diode is adequate. However,
the gains are modest. For a 5 V, 2 A design the external diode adds
~0.1% to full load efficiency at 85 VAC and ~0.2% at 230 VAC.
Figure 14. Acceptable FORWARD Pin Waveform After Handshake with
SR MOSFET Conduction During Flyback Cycle.
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The voltage rating of the Schottky diode and the SR FET should be at
least 1.4 times the expected peak inverse voltage (PIV) based on the
turns ratio used for the transformer. 60 V rated FETs and diodes are
suitable for most 5 V designs that use a VOR < 60 V, and 100 V rated
FETs and diodes are suitable for 12 V designs.
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Figure 15. Unacceptable FORWARD Pin Waveform before Handshake with Body
Diode Conduction During Flyback Cycle.
12
Rev. D 08/18
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