InnoSwitch3-CE
Recommendations for EMI Reduction
2. Higher VOR reduces the voltage stress on the output diodes and
SR MOSFETs.
3. Higher VOR increases leakage inductance which reduces power
supply efficiency.
4. Higher VOR increases peak and RMS current on the secondary-side
which may increase secondary-side copper and diode losses.
1. Appropriate component placement and small loop areas of the
primary and secondary power circuits help minimize radiated and
conducted EMI. Care should be taken to achieve a compact loop
area.
2. A small capacitor in parallel to the clamp diode on the primary-
side can help reduce radiated EMI.
3. A resistor in series with the bias winding helps reduce radiated EMI.
4. Common mode chokes are typically required at the input of the
power supply to sufficiently attenuate common mode noise.
However the same performance can be achieved by using shield
windings on the transformer. Shield windings can also be used in
conjunction with common mode filter inductors at input to
improve conducted and radiated EMI margins.
There are some exceptions to this. For very high output currents the
VOR should be reduced to get highest efficiency. For output voltages
above 15 V, VOR should be higher to maintain an acceptable PIV across
the output synchronous rectifier.
Ripple to Peak Current Ratio, KP
A KP below 1 indicates continuous conduction mode, where KP is the
ratio of ripple-current to peak-primary-current (Figure 18).
5. Adjusting SR MOSFET RC snubber component values can help
reduce high frequency radiated and conducted EMI.
6. A pi-filter comprising differential inductors and capacitors can be
used in the input rectifier circuit to reduce low frequency
differential EMI.
KP ≡ KRP = IR / IP
A value of KP higher than 1, indicates discontinuous conduction mode.
In this case KP is the ratio of primary MOSFET off-time to the
secondary diode conduction-time.
7. A 1 mF ceramic capacitor connected at the output of the power
supply helps to reduce radiated EMI.
KP ≡ KDP = (1 – D) x T/ t = VOR × (1 – DMAX) / ((VMIN – VDS) × DMAX
)
It is recommended that a KP close to 0.9 at the minimum expected DC
bus voltage should be used for most InnoSwitch3-CE designs. A KP
value of <1 results in higher transformer efficiency by lowering the
primary RMS current but results in higher switching losses in the
primary-side MOSFET resulting in higher InnoSwitch3-CE temperature.
The benefits of quasi-resonant switching start to diminish for a
further reduction of KP.
Recommendations for Transformer Design
Transformer design must ensure that the power supply delivers the
rated power at the lowest input voltage. The lowest voltage on the
rectified DC bus depends on the capacitance of the filter capacitor
used. At least 2 mF/W is recommended to always keep the DC bus
voltage above 70 V, though 3 mF/W provides sufficient margin. The
ripple on the DC bus should be measured to confirm the design
calculations for transformer primary-winding inductance selection.
For a typical USB PD and rapid charge designs which require a wide
output voltage range, KP will change significantly as the output
voltage changes. KP will be high for high output voltage conditions
and will drop as the output voltage is lowered. The PIXls spreadsheet
can be used to effectively optimize selection of KP, inductance of the
primary winding, transformer turns ratio, and the operating frequency
while ensuring appropriate design margins.
Switching Frequency (fSW
)
It is a unique feature in InnoSwitch3-CE that for full load, the designer
can set the switching frequency to between 25 kHz to 95 kHz. For
lowest temperature, the switching frequency should be set to around
60 kHz. For a smaller transformer, the full load switching frequency
needs to be set to 95 kHz. When setting the full load switching
frequency it is important to consider primary inductance and peak
current tolerances to ensure that average switching frequency does
not exceed 110 kHz which may trigger auto-restart due to overload
protection. The following table provides a guide to frequency
selection based on device size. This represents the best compromise
between overall device losses (conduction losses and switching
losses) based on the size of the integrated high-voltage MOSFET.
Core Type
Choice of a suitable core is dependent on the physical limits of the
power supply enclosure. It is recommended that only cores with low
loss be used to reduce thermal challenges.
Safety Margin, M (mm)
For designs that require safety isolation between primary and
secondary that are not using triple insulated wire, the width of the
safety margin to be used on each side of the bobbin is important.
For universal input designs a total margin of 6.2 mm is typically
required − 3.1 mm being used on either side of the winding. For
vertical bobbins the margin may not be symmetrical. However if a
total margin of 6.2 mm is required then the physical margin can be
placed on only one side of the bobbin. For designs using triple
insulated wire it may still be necessary to add a small margin in order
to meet required creepage distances. Many bobbins exist for each
core size and each will have different mechanical spacing. Refer to
the bobbin data sheet or seek guidance to determine what specific
margin is required. As the margin reduces the available area for the
windings, the winding area will disproportionately reduce for small
core sizes.
INN3162C and INN3163C
INN3164C and INN3165C
INN3166C
85-90 kHz
80 kHz
75 kHz
70 kHz
65 kHz
INN3167C
INN3168C
Reflected Output Voltage, VOR (V)
This parameter describes the effect on the primary MOSFET drain
voltage of the secondary-winding voltage during diode/SR conduction
which is reflected back to the primary through the turns ratio of the
transformer. To make full use of QR capability and ensure flattest
efficiency over line/load, set reflected output voltage (VOR) to
maintain KP = 0.8 at minimum input voltage for universal input and
KP = 1 for high-line-only conditions.
It is recommended that for compact power supply designs using an
InnoSwitch3-CE IC, triple insulated wire should be used.
Primary Layers, L
Primary layers should be in the range of 1 ≤ L ≤ 3 and in general
should be the lowest number that meets the primary current density
limit (CMA). A value of ≥200 Cmils / Amp can be used as a starting
point for most designs. Higher values may be required due to
thermal constraints. Designs with more than 3 layers are possible but
Consider the following for design optimization:
1. Higher VOR allows increased power delivery at VMIN, which
minimizes the value of the input capacitor and maximizes power
delivery from a given InnoSwitch3-CE device.
16
Rev. D 08/18
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