DPA422-426
Application Examples
C7
1 nF
R14
10 Ω
1.5 kV
L1
C11
C12
1 µF
10 V
C10
100 µF 100 µF
10 V 10 V
+
VIN
36-75 VDC
1 µH
2.5 A
L2
5 V, 6 A
C17
3300 pF
R1
619 kΩ
1%
R15
10 Ω
R17
R16
10 kΩ
D1
D2
BAV
Q1
10 Ω
19WS
Si4888
DY
RTN
T1
Q2
Si4888
DY
D4
BAV19WS
C4
4.7 µF
20 V
U2
R7
10 kΩ
R10
C1, C2 & C3
1 µF
100 V
10.0 kΩ
1%
DPA-Switch
U1
C16
D3
U2
PC357N1T
100 nF
D
L
BAV19WS
DPA425R
CONTROL
R6
150 Ω
R12
5.1 Ω
C
R9
220 Ω
S
X
F
C13
R4
C14
1 µF
10 µF
1.0 Ω
VR1
10 V
R3
C5
220 nF
SMBJ
150
U3
C6
68 µF
10 V
18.2 kΩ
R11
10.0 kΩ
1%
LM431AIM3
1%
VIN
PI-3472-040903
Figure 25. A High Efficiency 30 W, 5 V, Telecom Input DC-DC Converter.
High Efficiency 30 W Forward Converter
The selectable 300/400 kHz switching frequency is set to 300 kHz
by connecting the FREQUENCY (F) pin to CONTROL (C).
The circuit shown in Figure 25 is a typical implementation of a
single output DC-DC converter using DPA-Switch in a forward
configuration with synchronous rectification. This design
delivers 30 W at 5 V, from a 36 VDC to 75 VDC input with a
nominal efficiency at 48 VDC of 90% using the DPA425R.
DRAIN voltage clamping is provided by VR1, which keeps the
peak DRAIN voltage within acceptable limits. Transformer core
reset is provided by the gate capacitance of Q1 with R17 in
series. Optional reset capacitance C9 with R5 can be added if
necessary to supplement the gate capacitance of Q1.
By taking advantage of many of the built-in features of the
DPA-Switch, the design is greatly simplified compared to a
discrete implementation. Resistor R1 programs the input under-
voltage and overvoltage thresholds to typically 33 V and 86 V
respectively. This resistor also linearly reduces the maximum
duty from the internal maximum of 75% at 36 V to 42% at
72 V to prevent core saturation during load transients at high
input voltages. The DPA-Switch internal thresholds are
toleranced and characterized so the designer can guarantee
the converter will begin operation at 36 V, necessary to meet
ETSI standards, without the cost of an external reference IC.
The output of the transformer is rectified using MOSFETs to
provide synchronous rectification. The UV/OV function, together
with the turns ratio of the transformer, defines the maximum
MOSFET gate voltage, allowing the very simple gate drive
arrangement, without the need for drive windings or a drive IC.
During primary on-time, capacitor C17 couples charge through
resistor R15 to drive the gate of the forward MOSFET, Q2.
Capacitor C17 provides a DC isolated drive for Q2, preventing
gate overstress on Q1 during power down. The time constant
formed by R16 and C17 is selected to be much longer than one
switching cycle. Diode D4 resets the voltage on capacitor C17
before the next switching cycle. During the primary off-time, the
diode D2 provides a conduction path for the energy in inductor
L2 while Q1 is still off. The transformer reset voltage on the
secondary winding directly drives a positive voltage on the gate
of catch MOSFET, Q1. MOSFET Q1 provides a low loss
The current limit is externally set by resistor R3 to just above the
drain current level needed for maximum load regulation to limit
the maximum overload power of the converter. The externally
programmable current limit feature also allows a larger
DPA-Switch family member to be selected. Using the X pin, the
current limit can be adjusted to the same level. A large device
reduces conduction losses and improves efficiency without
requiring any other circuit changes. This has been used here to
replace the DPA424R with a DPA425R.
conduction path for a substantial portion of the primary off-time.
An isolated auxiliary winding on L2, rectified and filtered by D1
and C4, provides the bias supply for the optocoupler transistor.
14
Rev. T 12/12
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