DI-31
• Minimize primary and secondary high current loop areas
to reduce parasitic inductance.
TRANSFORMER PARAMETERS
• Optocoupler U2 should have a controlled CTR range of
100 to 200% for optimum loop stability.
EFD25, 3F3
Gap for ALG = 1100 nH/T2
Core Material
• Size transformer reset components to ensure transformer
reset at minimum operating voltage without exceeding
170 V drain voltage at high line. It may be necessary to gap
T1 to offset effect of Q4-Q6 gate capacitance.
• Set Zener VR1 clamp voltage to 150 V to both safely limit
the DRAIN below BVDSS and guarantee transformer reset.
• Select number of bias turns to provide 12 V to 14 V at
minimum input voltage and full load.
EFD25 10 pin
(B&B B-025 or equivalent)
Bobbin
Bias: 5T, 30 AWG
Primary: 6T+ 5T, 4 x 26 AWG
Secondary: 3T, 0.005" Cu foil
Winding Details
Primary (3-2), tape, Bias (4-5), tape,
Secondary (6,7-9,10), tape,
Primary (2-1), tape
Winding Order
(Pin Numbers)
• Main primary power return should be connected to the
DPA-Switch tab, not to the SOURCE pin.
Primary: 130 µH ±10%,
Leakge: 10 µH (max)
Inductance
• Scale time constant of C9 and L2 to allow C9 to reset
completely during minimum on-time conditions.
• Consult AN-31 for additional design tips and information.
Primary Resonant
Frequency
3 MHz (minimum)
Table 1. Transformer Design Parameters.
92
90
88
86
OUTPUT INDUCTOR PARAMETERS
EE22, TDK PC40 Material
Gap for ALG of 250 nH/T2
Core
Bobbin
TDK BE-22-5116
4T, 0.016" Cu foil
4 µH ± 10%
Winding Details
Inductance
84
82
80
VIN = 36 VDC
VIN = 48 VDC
VIN = 60 VDC
VIN = 72 VDC
Table 2. Output Inductor Construction Information.
0
20
40
60
80
Output Power (W)
Figure 2. Efficiency vs. Output Power.
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