Table 1. DPM Setup Registers
Address
1
Offset
0x00
0x04
0x08
0x09
0x0A
0x0B
0x0C
0x0D
0x0E
0x0F
0x10
0x11
0x13
0x15
0x17
0x1B
0x1F
0x23
0x27
0x28
0x80
0x84
0x88
0x89
0x8B
0x8C
0x8D
0x8E
0x8F
0x91
0x95
0x96
Register
Name
GD1[3:0]
GD2[3:0]
GAC
GBC
GCC
GDC
FPC1
FPC2
EPC
IC1
IC2
IBL[1:0]
IBH[1:0]
ID[1:0]
PB1[3:0]
PB2[3:0]
PB3[3:0]
PB4[3:0]
PMC
PID[31:0]
RTC[3:0]
PPS[3:0]
EST
IBV[1:0]
STA
STB
STC
STD
REL[1:0]
PSS[3:0]
DPMS
WP
Content
Group Definition Register 1
Group Definition Register 2
Group A Configuration
Group B Configuration
Group C Configuration
Group D Configuration
Fault Propagation Configuration 1
Fault Propagation Configuration 2
Error Propagation Configuration
Interrupt Configuration 1
Interrupt Configuration 2
IBV Low threshold
IBV high threshold
DPM Customer Identification
Parallel Bus Register 1
Parallel Bus Register 2
Parallel Bus Register 3
Parallel Bus Register 4
Power Manager Configuration
POL Identification Register
Run Time Counter
POL Programming Status
Event Status
IB Voltage
Status of Group A
Status of Group B
Status of Group C
Status of Group D
DPM Software Release
POL Status Summary
DPM Status
Write Protection
Register
Type
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Static
Run time
Run time
Run time
Run time
Run time
Run time
Run time
Run time
Static
Run time
Run time
Volatile
User
Access
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
OTP
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R
R
R
R/W
Write
Protect
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
yes
N/A
yes
yes
yes
yes
yes
yes
Read only
Initial Value
0x00000000
0x00000000
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0xFF
0xFFFF
0x00000000
0x00000000
0x00000000
0x00000000
0x00
0x00
value at last shut-down
(4x) 0x00
0x00
0x00
0x00
0x00
0x00
0x00
According to DPM type
0x00
0x01
0x00
______________________________________
1
Writing
into memory locations beyond address offset 0x96 must be avoided
The static registers are saved in the non-volatile memory and used to store the system configuration data. The run-
time registers contain status information and are evaluated during run-time. The Write Protection register WP is a
volatile register that defaults to write protect at power-up.
10.1.3
POL Setup Registers
Since the POL converters contain only RAM, the data defining performance parameters for each POL and Auxiliary
Device, such as the output voltage, protection thresholds, feedback loop compensation, turn-on and turn-off delays,
fault management settings, etc., is stored in the POL setup registers in the DPM. The POL setup registers consist of
23 data bytes and 2 CRC bytes. The Auxiliary Device setup registers occupy the same amount of bytes as a POL
converter, but only 3 registers have meaningful data. The other registers should be filled with 0x00. The POL setup
registers are listed in Table 2. Register significance is different in some cases between the new DP and older ZY series
POLs which are still supported. Differences are in
bold
for the DP series devices.
ZD-00896 Rev. 5.2, 9-Apr-13
www.power-one.com
Page 11 of 36
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