DFC15 Single-Output DC-DC Series Data Sheet
Input Parameters
(1)
Model
Voltage Range
Input Current
Full Load
No Load
MIN
TYP
MAX
T YP
T YP
TYP
T YP
MAX
T YP
5
DFC15U48S5
DFC15U48S12
20.0
48.0
60.0
91 5
4
82
120
75
10
DFC15U48S15
Units
VDC
905
4
83
mA
%
kHz
VDC
ms
Efficiency
Switching Frequency
Maximum Input Overvoltage, 100ms
No Damage
Turn-on Time, 1% Output Error
950
2
79
Output Parameters
(1)
Model
Output Voltage
Rated Load (3)
Voltage Range
100% Load
Load Regulation
25-100% Full Load
Line Regulation
Vin = Min-Max VDC
Short Term Stability (4)
Long Term Stability
Input Ripple Rejection (5)
Noise, 0-20MHz bw (2)
RMS Noise
Temperature Coefficient
Short Circuit Protection
+OUT to -OUT
MIN
MAX
MIN
T YP
MAX
T YP
MAX
TYP
MAX
T YP
TYP
TYP
TYP
TYP
T YP
MAX
75
3
DFC15U48S5
5
0
3000
4.95
5.00
5.05
0.5
0.75
0.1
0.15
DFC15U48S12
12
0
1 25 0
11.90
12.00
12.10
0.1
0.2
0.01
0.1
< 0.02
< 0.05
> 60
60
2
50
150
Continuous Current Limit
60
2
DFC15U48S15
15
0
10 0 0
14.90
15.00
15.10
0.1
0. 2
0.01
0.1
Units
VDC
mA
VDC
%
%
%/24Hrs
%/kHrs
dB
m V
P P
mV
rms
ppm/
°C
Notes
(1) All Parameters measured at Tc=25°C, nominal input voltage
and full rated load unless otherwise noted.
(2) Noise measurement bandwidth is 0-20 MHz. RMS noise is
measured over a 0.01-1 MHz bandwidth. To simulate standard
PCB decoupling practices, output noise is measured with a
1μF/35V tantalum capacitor located 1 inch away from the
converter.
(3) Minimum load required for rated regulation only. Dynamic
response may degrade if run at less than 25% full load.
(4) Short term stability is specified after a 30-minute warmup at full
load, and with constant line, load and ambient conditions.
(5) The input ripple rejection is specified for DC to 120 Hz ripple
with a modulation amplitude of 1% Vin.
MCD10177 Rev. 1.0, 16-Jun-10
Page 2 of 4
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